1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \ 3; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 4; We don't want to produce a CTR loop due to the call to lrint in the body. 5define dso_local void @test(i64 %arg, i64 %arg1) { 6; CHECK-LABEL: test: 7; CHECK: # %bb.0: # %bb 8; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_5 9; CHECK-NEXT: # %bb.1: # %bb3 10; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6 11; CHECK-NEXT: # %bb.2: # %bb4 12; CHECK-NEXT: mflr r0 13; CHECK-NEXT: .cfi_def_cfa_offset 64 14; CHECK-NEXT: .cfi_offset lr, 16 15; CHECK-NEXT: .cfi_offset r29, -24 16; CHECK-NEXT: .cfi_offset r30, -16 17; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill 18; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill 19; CHECK-NEXT: stdu r1, -64(r1) 20; CHECK-NEXT: sub r30, r4, r3 21; CHECK-NEXT: li r29, -4 22; CHECK-NEXT: std r0, 80(r1) 23; CHECK-NEXT: .p2align 5 24; CHECK-NEXT: .LBB0_3: # %bb5 25; CHECK-NEXT: # 26; CHECK-NEXT: lfsu f1, 4(r29) 27; CHECK-NEXT: bl lrint 28; CHECK-NEXT: nop 29; CHECK-NEXT: addi r30, r30, -1 30; CHECK-NEXT: cmpldi r30, 0 31; CHECK-NEXT: bc 12, gt, .LBB0_3 32; CHECK-NEXT: # %bb.4: # %bb15 33; CHECK-NEXT: stb r3, 0(r3) 34; CHECK-NEXT: addi r1, r1, 64 35; CHECK-NEXT: ld r0, 16(r1) 36; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload 37; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload 38; CHECK-NEXT: mtlr r0 39; CHECK-NEXT: blr 40; CHECK-NEXT: .LBB0_5: # %bb2 41; CHECK-NEXT: .LBB0_6: # %bb14 42bb: 43 br i1 undef, label %bb3, label %bb2 44 45bb2: ; preds = %bb 46 unreachable 47 48bb3: ; preds = %bb 49 %tmp = sub i64 %arg1, %arg 50 br i1 undef, label %bb4, label %bb14 51 52bb4: ; preds = %bb3 53 br label %bb5 54 55bb5: ; preds = %bb5, %bb4 56 %tmp6 = phi i64 [ %tmp12, %bb5 ], [ 0, %bb4 ] 57 %tmp7 = getelementptr inbounds float, ptr null, i64 %tmp6 58 %tmp8 = load float, ptr %tmp7, align 4 59 %tmp9 = fpext float %tmp8 to double 60 %tmp10 = tail call i64 @llvm.lrint.i64.f64(double %tmp9) #2 61 %tmp11 = trunc i64 %tmp10 to i8 62 store i8 %tmp11, ptr undef, align 1 63 %tmp12 = add nuw i64 %tmp6, 1 64 %tmp13 = icmp eq i64 %tmp12, %tmp 65 br i1 %tmp13, label %bb15, label %bb5 66 67bb14: ; preds = %bb3 68 unreachable 69 70bb15: ; preds = %bb5 71 ret void 72} 73 74declare i64 @llvm.lrint.i64.f64(double) 75