xref: /llvm-project/llvm/test/CodeGen/PowerPC/pr42492.ll (revision 5403c59c608c08c8ecd4303763f08eb046eb5e4d)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
3
4define void @f(ptr, ptr, ptr) {
5; Check we don't assert and this is not a Hardware Loop
6; CHECK-LABEL: f:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    cmpld 3, 4
9; CHECK-NEXT:    beqlr 0
10; CHECK-NEXT:  # %bb.1:
11; CHECK-NEXT:    not 3, 3
12; CHECK-NEXT:    add 3, 3, 4
13; CHECK-NEXT:    li 4, 15
14; CHECK-NEXT:    cmpldi 3, 15
15; CHECK-NEXT:    isellt 3, 3, 4
16; CHECK-NEXT:    addi 4, 3, 1
17; CHECK-NEXT:    ld 3, 8(5)
18; CHECK-NEXT:    mtctr 4
19; CHECK-NEXT:    .p2align 4
20; CHECK-NEXT:  .LBB0_2:
21; CHECK-NEXT:    sldi 3, 3, 4
22; CHECK-NEXT:    bdnz .LBB0_2
23; CHECK-NEXT:  # %bb.3:
24; CHECK-NEXT:    std 3, 8(5)
25; CHECK-NEXT:    blr
26
27  %4 = icmp eq ptr %0, %1
28  br i1 %4, label %9, label %5
29
305:                                                ; preds = %3
31  %6 = getelementptr inbounds i64, ptr %2, i64 1
32  %7 = load i64, ptr %6, align 8
33  br label %10
34
358:                                                ; preds = %10
36  store i64 %14, ptr %6, align 8
37  br label %9
38
399:                                                ; preds = %8, %3
40  ret void
41
4210:                                               ; preds = %5, %10
43  %11 = phi i64 [ %7, %5 ], [ %14, %10 ]
44  %12 = phi i32 [ 0, %5 ], [ %15, %10 ]
45  %13 = phi ptr [ %0, %5 ], [ %16, %10 ]
46  %14 = shl nsw i64 %11, 4
47  %15 = add nuw nsw i32 %12, 1
48  %16 = getelementptr inbounds i8, ptr %13, i64 1
49  %17 = icmp ugt i32 %12, 14
50  %18 = icmp eq ptr %16, %1
51  %19 = or i1 %18, %17
52  br i1 %19, label %8, label %10
53}
54