xref: /llvm-project/llvm/test/CodeGen/PowerPC/pr38087.ll (revision b1a48af56a62b8c0d5636c9404251700264fcd70)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
3; RUN:   -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names < %s | \
4; RUN:   FileCheck %s
5; Function Attrs: nounwind readnone speculatable
6declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0
7
8; Function Attrs: nounwind readnone speculatable
9declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #0
10
11define void @draw_llvm_vs_variant0(<4 x float> %x) {
12; CHECK-LABEL: draw_llvm_vs_variant0:
13; CHECK:       # %bb.0: # %entry
14; CHECK-NEXT:    lxsihzx v3, 0, r3
15; CHECK-NEXT:    vextsh2w v3, v3
16; CHECK-NEXT:    xxmrghw v3, v3, v3
17; CHECK-NEXT:    xvcvsxwsp vs0, v3
18; CHECK-NEXT:    xxspltw vs0, vs0, 2
19; CHECK-NEXT:    xvmaddasp vs0, v2, v2
20; CHECK-NEXT:    stxv vs0, 0(r3)
21; CHECK-NEXT:    blr
22entry:
23  %.size = load i32, ptr undef
24  %0 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %.size, i32 7)
25  %1 = extractvalue { i32, i1 } %0, 0
26  %2 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %1, i32 0)
27  %3 = extractvalue { i32, i1 } %2, 0
28  %4 = select i1 false, i32 0, i32 %3
29  %5 = xor i1 false, true
30  %6 = sext i1 %5 to i32
31  %7 = load <4 x i16>, ptr undef, align 2
32  %8 = extractelement <4 x i16> %7, i32 0
33  %9 = sext i16 %8 to i32
34  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
35  %11 = extractelement <4 x i16> %7, i32 1
36  %12 = sext i16 %11 to i32
37  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
38  %14 = extractelement <4 x i16> %7, i32 2
39  %15 = sext i16 %14 to i32
40  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
41  %17 = extractelement <4 x i16> %7, i32 3
42  %18 = sext i16 %17 to i32
43  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
44  %20 = sitofp <4 x i32> %19 to <4 x float>
45  %21 = insertelement <4 x i32> undef, i32 %6, i32 0
46  %22 = shufflevector <4 x i32> %21, <4 x i32> undef, <4 x i32> zeroinitializer
47  %23 = bitcast <4 x float> %20 to <4 x i32>
48  %24 = and <4 x i32> %23, %22
49  %25 = bitcast <4 x i32> %24 to <4 x float>
50  %26 = shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
51  %27 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %x, <4 x float> %x, <4 x float> %26)
52  store <4 x float> %27, ptr undef
53  ret void
54}
55