xref: /llvm-project/llvm/test/CodeGen/PowerPC/pr116071.ll (revision 4d06623b28ab373cd5438fda6c79cf62fc53ace0)
1; RUN: llc -disable-ppc-vsx-fma-mutation=false -mcpu=pwr10 -verify-machineinstrs \
2; RUN:   -ppc-asm-full-reg-names -mtriple powerpc64-ibm-aix7.2.0.0 < %s | FileCheck %s
3
4target datalayout = "E-m:a-Fi64-i64:64-n32:64-S128-v256:256:256-v512:512:512"
5
6define void @initial(<2 x double> %0){
7entry:
8  %1 = fmul <2 x double> %0, zeroinitializer
9  br label %for.cond251.preheader.lr.ph
10
11for.cond251.preheader.lr.ph:                      ; preds = %for.cond251.preheader.lr.ph, %entry
12  %2 = phi double [ %3, %for.cond251.preheader.lr.ph ], [ 0.000000e+00, %entry ]
13  %3 = phi double [ %7, %for.cond251.preheader.lr.ph ], [ 0.000000e+00, %entry ]
14  %add737 = fadd double %3, %2
15  %4 = insertelement <2 x double> zeroinitializer, double %add737, i64 0
16  %5 = fmul contract <2 x double> %4, zeroinitializer
17  %6 = fadd contract <2 x double> %1, %5
18  %7 = extractelement <2 x double> %6, i64 0
19  br label %for.cond251.preheader.lr.ph
20}
21
22; CHECK:        xsadddp f4, f3, f4
23; CHECK-NEXT:   xxmrghd vs5, vs4, vs2
24; CHECK-NEXT:   fmr f4, f3
25; CHECK-NEXT:   xvmaddmdp vs5, vs0, vs1
26; CHECK-NEXT:   fmr f3, f5
27