xref: /llvm-project/llvm/test/CodeGen/PowerPC/ppc64-varargs.ll (revision a51712751c184ebe056718c938d2526693a31564)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64 \
3; RUN:   < %s | FileCheck --check-prefix=BE %s
4; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mtriple=powerpc64le \
5; RUN:   < %s | FileCheck --check-prefix=LE %s
6
7define i32 @f(...) nounwind {
8; BE-LABEL: f:
9; BE:       # %bb.0: # %entry
10; BE-NEXT:    li r3, 0
11; BE-NEXT:    blr
12;
13; LE-LABEL: f:
14; LE:       # %bb.0: # %entry
15; LE-NEXT:    li r3, 0
16; LE-NEXT:    blr
17entry:
18  ret i32 0
19}
20
21define i32 @f1(...) nounwind {
22; BE-LABEL: f1:
23; BE:       # %bb.0: # %entry
24; BE-NEXT:    mr r11, r3
25; BE-NEXT:    addi r12, r1, 48
26; BE-NEXT:    li r3, 0
27; BE-NEXT:    std r11, 48(r1)
28; BE-NEXT:    std r4, 56(r1)
29; BE-NEXT:    std r5, 64(r1)
30; BE-NEXT:    std r6, 72(r1)
31; BE-NEXT:    std r7, 80(r1)
32; BE-NEXT:    std r8, 88(r1)
33; BE-NEXT:    std r9, 96(r1)
34; BE-NEXT:    std r10, 104(r1)
35; BE-NEXT:    std r12, -8(r1)
36; BE-NEXT:    blr
37;
38; LE-LABEL: f1:
39; LE:       # %bb.0: # %entry
40; LE-NEXT:    std r3, 32(r1)
41; LE-NEXT:    addi r3, r1, 32
42; LE-NEXT:    std r4, 40(r1)
43; LE-NEXT:    std r5, 48(r1)
44; LE-NEXT:    std r6, 56(r1)
45; LE-NEXT:    std r7, 64(r1)
46; LE-NEXT:    std r8, 72(r1)
47; LE-NEXT:    std r9, 80(r1)
48; LE-NEXT:    std r3, -8(r1)
49; LE-NEXT:    li r3, 0
50; LE-NEXT:    std r10, 88(r1)
51; LE-NEXT:    blr
52entry:
53  %va = alloca ptr, align 8
54  call void @llvm.va_start(ptr %va)
55  ret i32 0
56}
57
58declare void @llvm.va_start(ptr) nounwind
59