xref: /llvm-project/llvm/test/CodeGen/PowerPC/ppc64-byval-align.ll (revision 5403c59c608c08c8ecd4303763f08eb046eb5e4d)
1; RUN: llc -verify-machineinstrs -O1 < %s -mcpu=pwr7 | FileCheck %s
2
3target datalayout = "E-m:e-i64:64-n32:64"
4target triple = "powerpc64-unknown-linux-gnu"
5
6%struct.test = type { i64, [8 x i8] }
7%struct.pad = type { [8 x i64] }
8
9@gt = common global %struct.test zeroinitializer, align 16
10@gp = common global %struct.pad zeroinitializer, align 8
11
12define signext i32 @callee1(i32 signext %x, ptr byval(%struct.test) align 16 nocapture readnone %y, i32 signext %z) {
13entry:
14  ret i32 %z
15}
16; CHECK-LABEL: @callee1
17; CHECK: mr 3, 7
18; CHECK: blr
19
20declare signext i32 @test1(i32 signext, ptr byval(%struct.test) align 16, i32 signext)
21define void @caller1(i32 signext %z) {
22entry:
23  %call = tail call signext i32 @test1(i32 signext 0, ptr byval(%struct.test) align 16 @gt, i32 signext %z)
24  ret void
25}
26; CHECK-LABEL: @caller1
27; CHECK: mr 7, 3
28; CHECK: bl test1
29
30define i64 @callee2(ptr byval(%struct.pad) nocapture readnone %x, i32 signext %y, ptr byval(%struct.test) align 16 nocapture readonly %z) {
31entry:
32  %0 = load i64, ptr %z, align 16
33  ret i64 %0
34}
35; CHECK-LABEL: @callee2
36; CHECK: ld {{[0-9]+}}, 128(1)
37; CHECK: blr
38
39declare i64 @test2(ptr byval(%struct.pad), i32 signext, ptr byval(%struct.test) align 16)
40define void @caller2(i64 %z) {
41entry:
42  %tmp = alloca %struct.test, align 16
43  store i64 %z, ptr %tmp, align 16
44  %call = call i64 @test2(ptr byval(%struct.pad) @gp, i32 signext 0, ptr byval(%struct.test) align 16 %tmp)
45  ret void
46}
47; CHECK-LABEL: @caller2
48; CHECK-DAG: std 3, [[OFF:[0-9]+]](1)
49; CHECK-DAG: addi [[REG1:[0-9]+]], 1, [[OFF]]
50;
51; CHECK-DAG: lxvw4x [[REG2:[0-9]+]], 0, [[REG1]]
52; CHECK-DAG: li [[REG3:[0-9]+]], 128
53; CHECK:     stxvw4x 0, 1, [[REG3]]
54; CHECK:     bl test2
55
56