xref: /llvm-project/llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll (revision 898b8a42b5fde2738da46ec9f5b427693bc681a1) 
1; RUN: llc -verify-machineinstrs < %s | FileCheck %s
2; RUN: llc -mcpu=pwr10 -verify-machineinstrs < %s | FileCheck %s
3target datalayout = "E-m:e-i64:64-n32:64"
4target triple = "powerpc64-unknown-linux-gnu"
5
6; CHECK-LABEL: test:
7; CHECK: {{^}}.L[[test_BEGIN:.*]]:{{$}}
8
9; CHECK-LABEL: property_access1:
10; CHECK: {{^}}.L[[property_access1_BEGIN:.*]]:{{$}}
11
12; CHECK-LABEL: property_access2:
13; CHECK: {{^}}.L[[property_access2_BEGIN:.*]]:{{$}}
14
15; CHECK-LABEL: property_access3:
16; CHECK: {{^}}.L[[property_access3_BEGIN:.*]]:{{$}}
17
18; CHECK-LABEL: anyreg_test1:
19; CHECK: {{^}}.L[[anyreg_test1_BEGIN:.*]]:{{$}}
20
21; CHECK-LABEL: anyreg_test2:
22; CHECK: {{^}}.L[[anyreg_test2_BEGIN:.*]]:{{$}}
23
24; CHECK-LABEL: patchpoint_spilldef:
25; CHECK: {{^}}.L[[patchpoint_spilldef_BEGIN:.*]]:{{$}}
26
27; CHECK-LABEL: patchpoint_spillargs:
28; CHECK: {{^}}.L[[patchpoint_spillargs_BEGIN:.*]]:{{$}}
29
30
31; Stackmap Header: no constants - 6 callsites
32; CHECK-LABEL: .section	.llvm_stackmaps
33; CHECK-NEXT:  __LLVM_StackMaps:
34; Header
35; CHECK-NEXT:   .byte 3
36; CHECK-NEXT:   .byte 0
37; CHECK-NEXT:   .short 0
38; Num Functions
39; CHECK-NEXT:   .long 8
40; Num LargeConstants
41; CHECK-NEXT:   .long 0
42; Num Callsites
43; CHECK-NEXT:   .long 8
44
45; Functions and stack size
46; CHECK-NEXT:   .quad test
47; CHECK-NEXT:   .quad 128
48; CHECK-NEXT:   .quad 1
49; CHECK-NEXT:   .quad property_access1
50; CHECK-NEXT:   .quad 128
51; CHECK-NEXT:   .quad 1
52; CHECK-NEXT:   .quad property_access2
53; CHECK-NEXT:   .quad 128
54; CHECK-NEXT:   .quad 1
55; CHECK-NEXT:   .quad property_access3
56; CHECK-NEXT:   .quad 128
57; CHECK-NEXT:   .quad 1
58; CHECK-NEXT:   .quad anyreg_test1
59; CHECK-NEXT:   .quad 144
60; CHECK-NEXT:   .quad 1
61; CHECK-NEXT:   .quad anyreg_test2
62; CHECK-NEXT:   .quad 144
63; CHECK-NEXT:   .quad 1
64; CHECK-NEXT:   .quad patchpoint_spilldef
65; CHECK-NEXT:   .quad 256
66; CHECK-NEXT:   .quad 1
67; CHECK-NEXT:   .quad patchpoint_spillargs
68; CHECK-NEXT:   .quad 288
69; CHECK-NEXT:   .quad 1
70
71
72; test
73; CHECK:  .long   .L{{.*}}-.L[[test_BEGIN]]
74; CHECK-NEXT:   .short  0
75; 3 locations
76; CHECK-NEXT:   .short  3
77; Loc 0: Register
78; CHECK-NEXT:   .byte 1
79; CHECK-NEXT:   .byte 0
80; CHECK-NEXT:   .short 4
81; CHECK-NEXT:   .short {{[0-9]+}}
82; CHECK-NEXT:   .short 0
83; CHECK-NEXT:   .long 0
84; Loc 1: Register
85; CHECK-NEXT:   .byte 1
86; CHECK-NEXT:   .byte 0
87; CHECK-NEXT:   .short 4
88; CHECK-NEXT:   .short {{[0-9]+}}
89; CHECK-NEXT:   .short 0
90; CHECK-NEXT:   .long 0
91; Loc 2: Constant 3
92; CHECK-NEXT:   .byte 4
93; CHECK-NEXT:   .byte 0
94; CHECK-NEXT:   .short 8
95; CHECK-NEXT:   .short 0
96; CHECK-NEXT:   .short 0
97; CHECK-NEXT:   .long 3
98define i64 @test() nounwind ssp uwtable {
99entry:
100  call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 40, ptr null, i32 2, i32 1, i32 2, i64 3)
101  ret i64 0
102}
103
104; property access 1 - %obj is an anyreg call argument and should therefore be in a register
105; CHECK:  .long   .L{{.*}}-.L[[property_access1_BEGIN]]
106; CHECK-NEXT:   .short 0
107; 2 locations
108; CHECK-NEXT:   .short  2
109; Loc 0: Register <-- this is the return register
110; CHECK-NEXT:   .byte 1
111; CHECK-NEXT:   .byte 0
112; CHECK-NEXT:   .short 8
113; CHECK-NEXT:   .short {{[0-9]+}}
114; CHECK-NEXT:   .short 0
115; CHECK-NEXT:   .long 0
116; Loc 1: Register
117; CHECK-NEXT:   .byte 1
118; CHECK-NEXT:   .byte 0
119; CHECK-NEXT:   .short 8
120; CHECK-NEXT:   .short {{[0-9]+}}
121; CHECK-NEXT:   .short 0
122; CHECK-NEXT:   .long 0
123define i64 @property_access1(ptr %obj) nounwind ssp uwtable {
124entry:
125  %f = inttoptr i64 281474417671919 to ptr
126  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 40, ptr %f, i32 1, ptr %obj)
127  ret i64 %ret
128}
129
130; property access 2 - %obj is an anyreg call argument and should therefore be in a register
131; CHECK:  .long   .L{{.*}}-.L[[property_access2_BEGIN]]
132; CHECK-NEXT:   .short 0
133; 2 locations
134; CHECK-NEXT:   .short  2
135; Loc 0: Register <-- this is the return register
136; CHECK-NEXT:   .byte 1
137; CHECK-NEXT:   .byte 0
138; CHECK-NEXT:   .short 8
139; CHECK-NEXT:   .short {{[0-9]+}}
140; CHECK-NEXT:   .short 0
141; CHECK-NEXT:   .long 0
142; Loc 1: Register
143; CHECK-NEXT:   .byte 1
144; CHECK-NEXT:   .byte 0
145; CHECK-NEXT:   .short 8
146; CHECK-NEXT:   .short {{[0-9]+}}
147; CHECK-NEXT:   .short 0
148; CHECK-NEXT:   .long 0
149define i64 @property_access2() nounwind ssp uwtable {
150entry:
151  %obj = alloca i64, align 8
152  %f = inttoptr i64 281474417671919 to ptr
153  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 40, ptr %f, i32 1, ptr %obj)
154  ret i64 %ret
155}
156
157; property access 3 - %obj is a frame index
158; CHECK:  .long   .L{{.*}}-.L[[property_access3_BEGIN]]
159; CHECK-NEXT:   .short 0
160; 2 locations
161; CHECK-NEXT:   .short  2
162; Loc 0: Register <-- this is the return register
163; CHECK-NEXT:   .byte 1
164; CHECK-NEXT:   .byte 0
165; CHECK-NEXT:   .short 8
166; CHECK-NEXT:   .short {{[0-9]+}}
167; CHECK-NEXT:   .short 0
168; CHECK-NEXT:   .long 0
169; Loc 1: Direct FP - 8
170; CHECK-NEXT:   .byte 2
171; CHECK-NEXT:   .byte 0
172; CHECK-NEXT:   .short 8
173; CHECK-NEXT:   .short 31
174; CHECK-NEXT:   .short 0
175; CHECK-NEXT:   .long 112
176define i64 @property_access3() nounwind ssp uwtable {
177entry:
178  %obj = alloca i64, align 8
179  %f = inttoptr i64 281474417671919 to ptr
180  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 40, ptr %f, i32 0, ptr %obj)
181  ret i64 %ret
182}
183
184; anyreg_test1
185; CHECK:  .long   .L{{.*}}-.L[[anyreg_test1_BEGIN]]
186; CHECK-NEXT:   .short 0
187; 14 locations
188; CHECK-NEXT:   .short  14
189; Loc 0: Register <-- this is the return register
190; CHECK-NEXT:   .byte 1
191; CHECK-NEXT:   .byte 0
192; CHECK-NEXT:   .short 8
193; CHECK-NEXT:   .short {{[0-9]+}}
194; CHECK-NEXT:   .short 0
195; CHECK-NEXT:   .long 0
196; Loc 1: Register
197; CHECK-NEXT:   .byte 1
198; CHECK-NEXT:   .byte 0
199; CHECK-NEXT:   .short 8
200; CHECK-NEXT:   .short {{[0-9]+}}
201; CHECK-NEXT:   .short 0
202; CHECK-NEXT:   .long 0
203; Loc 2: Register
204; CHECK-NEXT:   .byte 1
205; CHECK-NEXT:   .byte 0
206; CHECK-NEXT:   .short 8
207; CHECK-NEXT:   .short {{[0-9]+}}
208; CHECK-NEXT:   .short 0
209; CHECK-NEXT:   .long 0
210; Loc 3: Register
211; CHECK-NEXT:   .byte 1
212; CHECK-NEXT:   .byte 0
213; CHECK-NEXT:   .short 8
214; CHECK-NEXT:   .short {{[0-9]+}}
215; CHECK-NEXT:   .short 0
216; CHECK-NEXT:   .long 0
217; Loc 4: Register
218; CHECK-NEXT:   .byte 1
219; CHECK-NEXT:   .byte 0
220; CHECK-NEXT:   .short 8
221; CHECK-NEXT:   .short {{[0-9]+}}
222; CHECK-NEXT:   .short 0
223; CHECK-NEXT:   .long 0
224; Loc 5: Register
225; CHECK-NEXT:   .byte 1
226; CHECK-NEXT:   .byte 0
227; CHECK-NEXT:   .short 8
228; CHECK-NEXT:   .short {{[0-9]+}}
229; CHECK-NEXT:   .short 0
230; CHECK-NEXT:   .long 0
231; Loc 6: Register
232; CHECK-NEXT:   .byte 1
233; CHECK-NEXT:   .byte 0
234; CHECK-NEXT:   .short 8
235; CHECK-NEXT:   .short {{[0-9]+}}
236; CHECK-NEXT:   .short 0
237; CHECK-NEXT:   .long 0
238; Loc 7: Register
239; CHECK-NEXT:   .byte 1
240; CHECK-NEXT:   .byte 0
241; CHECK-NEXT:   .short 8
242; CHECK-NEXT:   .short {{[0-9]+}}
243; CHECK-NEXT:   .short 0
244; CHECK-NEXT:   .long 0
245; Loc 8: Register
246; CHECK-NEXT:   .byte 1
247; CHECK-NEXT:   .byte 0
248; CHECK-NEXT:   .short 8
249; CHECK-NEXT:   .short {{[0-9]+}}
250; CHECK-NEXT:   .short 0
251; CHECK-NEXT:   .long 0
252; Loc 9: Register
253; CHECK-NEXT:   .byte 1
254; CHECK-NEXT:   .byte 0
255; CHECK-NEXT:   .short 8
256; CHECK-NEXT:   .short {{[0-9]+}}
257; CHECK-NEXT:   .short 0
258; CHECK-NEXT:   .long 0
259; Loc 10: Register
260; CHECK-NEXT:   .byte 1
261; CHECK-NEXT:   .byte 0
262; CHECK-NEXT:   .short 8
263; CHECK-NEXT:   .short {{[0-9]+}}
264; CHECK-NEXT:   .short 0
265; CHECK-NEXT:   .long 0
266; Loc 11: Register
267; CHECK-NEXT:   .byte 1
268; CHECK-NEXT:   .byte 0
269; CHECK-NEXT:   .short 8
270; CHECK-NEXT:   .short {{[0-9]+}}
271; CHECK-NEXT:   .short 0
272; CHECK-NEXT:   .long 0
273; Loc 12: Register
274; CHECK-NEXT:   .byte 1
275; CHECK-NEXT:   .byte 0
276; CHECK-NEXT:   .short 8
277; CHECK-NEXT:   .short {{[0-9]+}}
278; CHECK-NEXT:   .short 0
279; CHECK-NEXT:   .long 0
280; Loc 13: Register
281; CHECK-NEXT:   .byte 1
282; CHECK-NEXT:   .byte 0
283; CHECK-NEXT:   .short 8
284; CHECK-NEXT:   .short {{[0-9]+}}
285; CHECK-NEXT:   .short 0
286; CHECK-NEXT:   .long 0
287define i64 @anyreg_test1(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {
288entry:
289  %f = inttoptr i64 281474417671919 to ptr
290  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 40, ptr %f, i32 13, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)
291  ret i64 %ret
292}
293
294; anyreg_test2
295; CHECK:  .long   .L{{.*}}-.L[[anyreg_test2_BEGIN]]
296; CHECK-NEXT:   .short 0
297; 14 locations
298; CHECK-NEXT:   .short  14
299; Loc 0: Register <-- this is the return register
300; CHECK-NEXT:   .byte 1
301; CHECK-NEXT:   .byte 0
302; CHECK-NEXT:   .short 8
303; CHECK-NEXT:   .short {{[0-9]+}}
304; CHECK-NEXT:   .short 0
305; CHECK-NEXT:   .long 0
306; Loc 1: Register
307; CHECK-NEXT:   .byte 1
308; CHECK-NEXT:   .byte 0
309; CHECK-NEXT:   .short 8
310; CHECK-NEXT:   .short {{[0-9]+}}
311; CHECK-NEXT:   .short 0
312; CHECK-NEXT:   .long 0
313; Loc 2: Register
314; CHECK-NEXT:   .byte 1
315; CHECK-NEXT:   .byte 0
316; CHECK-NEXT:   .short 8
317; CHECK-NEXT:   .short {{[0-9]+}}
318; CHECK-NEXT:   .short 0
319; CHECK-NEXT:   .long 0
320; Loc 3: Register
321; CHECK-NEXT:   .byte 1
322; CHECK-NEXT:   .byte 0
323; CHECK-NEXT:   .short 8
324; CHECK-NEXT:   .short {{[0-9]+}}
325; CHECK-NEXT:   .short 0
326; CHECK-NEXT:   .long 0
327; Loc 4: Register
328; CHECK-NEXT:   .byte 1
329; CHECK-NEXT:   .byte 0
330; CHECK-NEXT:   .short 8
331; CHECK-NEXT:   .short {{[0-9]+}}
332; CHECK-NEXT:   .short 0
333; CHECK-NEXT:   .long 0
334; Loc 5: Register
335; CHECK-NEXT:   .byte 1
336; CHECK-NEXT:   .byte 0
337; CHECK-NEXT:   .short 8
338; CHECK-NEXT:   .short {{[0-9]+}}
339; CHECK-NEXT:   .short 0
340; CHECK-NEXT:   .long 0
341; Loc 6: Register
342; CHECK-NEXT:   .byte 1
343; CHECK-NEXT:   .byte 0
344; CHECK-NEXT:   .short 8
345; CHECK-NEXT:   .short {{[0-9]+}}
346; CHECK-NEXT:   .short 0
347; CHECK-NEXT:   .long 0
348; Loc 7: Register
349; CHECK-NEXT:   .byte 1
350; CHECK-NEXT:   .byte 0
351; CHECK-NEXT:   .short 8
352; CHECK-NEXT:   .short {{[0-9]+}}
353; CHECK-NEXT:   .short 0
354; CHECK-NEXT:   .long 0
355; Loc 8: Register
356; CHECK-NEXT:   .byte 1
357; CHECK-NEXT:   .byte 0
358; CHECK-NEXT:   .short 8
359; CHECK-NEXT:   .short {{[0-9]+}}
360; CHECK-NEXT:   .short 0
361; CHECK-NEXT:   .long 0
362; Loc 9: Register
363; CHECK-NEXT:   .byte 1
364; CHECK-NEXT:   .byte 0
365; CHECK-NEXT:   .short 8
366; CHECK-NEXT:   .short {{[0-9]+}}
367; CHECK-NEXT:   .short 0
368; CHECK-NEXT:   .long 0
369; Loc 10: Register
370; CHECK-NEXT:   .byte 1
371; CHECK-NEXT:   .byte 0
372; CHECK-NEXT:   .short 8
373; CHECK-NEXT:   .short {{[0-9]+}}
374; CHECK-NEXT:   .short 0
375; CHECK-NEXT:   .long 0
376; Loc 11: Register
377; CHECK-NEXT:   .byte 1
378; CHECK-NEXT:   .byte 0
379; CHECK-NEXT:   .short 8
380; CHECK-NEXT:   .short {{[0-9]+}}
381; CHECK-NEXT:   .short 0
382; CHECK-NEXT:   .long 0
383; Loc 12: Register
384; CHECK-NEXT:   .byte 1
385; CHECK-NEXT:   .byte 0
386; CHECK-NEXT:   .short 8
387; CHECK-NEXT:   .short {{[0-9]+}}
388; CHECK-NEXT:   .short 0
389; CHECK-NEXT:   .long 0
390; Loc 13: Register
391; CHECK-NEXT:   .byte 1
392; CHECK-NEXT:   .byte 0
393; CHECK-NEXT:   .short 8
394; CHECK-NEXT:   .short {{[0-9]+}}
395; CHECK-NEXT:   .short 0
396; CHECK-NEXT:   .long 0
397define i64 @anyreg_test2(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {
398entry:
399  %f = inttoptr i64 281474417671919 to ptr
400  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, ptr %f, i32 8, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)
401  ret i64 %ret
402}
403
404; Test spilling the return value of an anyregcc call.
405;
406; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
407;
408; CHECK: .long .L{{.*}}-.L[[patchpoint_spilldef_BEGIN]]
409; CHECK-NEXT: .short 0
410; CHECK-NEXT: .short 3
411; Loc 0: Register (some register that will be spilled to the stack)
412; CHECK-NEXT: .byte  1
413; CHECK-NEXT: .byte 0
414; CHECK-NEXT: .short 8
415; CHECK-NEXT: .short {{[0-9]+}}
416; CHECK-NEXT: .short 0
417; CHECK-NEXT: .long  0
418; Loc 1: Register
419; CHECK-NEXT: .byte  1
420; CHECK-NEXT: .byte 0
421; CHECK-NEXT: .short 8
422; CHECK-NEXT: .short {{[0-9]+}}
423; CHECK-NEXT: .short 0
424; CHECK-NEXT: .long  0
425; Loc 1: Register
426; CHECK-NEXT: .byte  1
427; CHECK-NEXT: .byte 0
428; CHECK-NEXT: .short 8
429; CHECK-NEXT: .short {{[0-9]+}}
430; CHECK-NEXT: .short 0
431; CHECK-NEXT: .long  0
432define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
433entry:
434  %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 40, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2)
435  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
436},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
437  ret i64 %result
438}
439
440; Test spilling the arguments of an anyregcc call.
441;
442; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
443;
444; CHECK: .long .L{{.*}}-.L[[patchpoint_spillargs_BEGIN]]
445; CHECK-NEXT: .short 0
446; CHECK-NEXT: .short 5
447; Loc 0: Return a register
448; CHECK-NEXT: .byte  1
449; CHECK-NEXT: .byte 0
450; CHECK-NEXT: .short 8
451; CHECK-NEXT: .short {{[0-9]+}}
452; CHECK-NEXT: .short 0
453; CHECK-NEXT: .long  0
454; Loc 1: Arg0 in a Register
455; CHECK-NEXT: .byte  1
456; CHECK-NEXT: .byte 0
457; CHECK-NEXT: .short 8
458; CHECK-NEXT: .short {{[0-9]+}}
459; CHECK-NEXT: .short 0
460; CHECK-NEXT: .long  0
461; Loc 2: Arg1 in a Register
462; CHECK-NEXT: .byte  1
463; CHECK-NEXT: .byte 0
464; CHECK-NEXT: .short 8
465; CHECK-NEXT: .short {{[0-9]+}}
466; CHECK-NEXT: .short 0
467; CHECK-NEXT: .long  0
468; Loc 3: Arg2 spilled to FP -96
469; CHECK-NEXT: .byte  3
470; CHECK-NEXT: .byte 0
471; CHECK-NEXT: .short 8
472; CHECK-NEXT: .short 31
473; CHECK-NEXT: .short 0
474; CHECK-NEXT: .long 128
475; Loc 4: Arg3 spilled to FP - 88
476; CHECK-NEXT: .byte  3
477; CHECK-NEXT: .byte 0
478; CHECK-NEXT: .short 8
479; CHECK-NEXT: .short 31
480; CHECK-NEXT: .short 0
481; CHECK-NEXT: .long 136
482define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
483entry:
484  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
485},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
486  %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 40, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
487  ret i64 %result
488}
489
490declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
491declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)
492