xref: /llvm-project/llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll (revision ff9af4c43ad71eeba2cabe99609cfaa0fd54c1d0)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc -mcpu=pwr7 < %s | FileCheck %s
3
4; This piece of IR is expanded from memcmp.
5define i1 @cmp(ptr %a, ptr %b) {
6; CHECK-LABEL: cmp:
7; CHECK:       # %bb.0: # %entry
8; CHECK-NEXT:    lwz 5, 4(3)
9; CHECK-NEXT:    lwz 7, 0(3)
10; CHECK-NEXT:    lwz 6, 4(4)
11; CHECK-NEXT:    lwz 8, 0(4)
12; CHECK-NEXT:    xor 9, 7, 8
13; CHECK-NEXT:    xor 10, 5, 6
14; CHECK-NEXT:    or. 9, 10, 9
15; CHECK-NEXT:    bne 0, .LBB0_2
16; CHECK-NEXT:  # %bb.1: # %loadbb1
17; CHECK-NEXT:    lbz 3, 8(3)
18; CHECK-NEXT:    lbz 4, 8(4)
19; CHECK-NEXT:    sub 3, 3, 4
20; CHECK-NEXT:    srwi 3, 3, 31
21; CHECK-NEXT:    blr
22; CHECK-NEXT:  .LBB0_2: # %res_block
23; CHECK-NEXT:    cmplw 7, 8
24; CHECK-NEXT:    cmplw 1, 5, 6
25; CHECK-NEXT:    li 3, 1
26; CHECK-NEXT:    li 4, -1
27; CHECK-NEXT:    crandc 20, 0, 2
28; CHECK-NEXT:    crand 21, 2, 4
29; CHECK-NEXT:    cror 20, 21, 20
30; CHECK-NEXT:    isel 3, 4, 3, 20
31; CHECK-NEXT:    srwi 3, 3, 31
32; CHECK-NEXT:    blr
33entry:
34  br label %loadbb
35
36res_block:
37  %0 = icmp ult i64 %4, %5
38  %1 = select i1 %0, i32 -1, i32 1
39  br label %endblock
40
41loadbb:
42  %2 = bitcast ptr %a to ptr
43  %3 = bitcast ptr %b to ptr
44  %4 = load i64, ptr %2, align 1
45  %5 = load i64, ptr %3, align 1
46  %6 = icmp eq i64 %4, %5
47  br i1 %6, label %loadbb1, label %res_block
48
49loadbb1:
50  %7 = getelementptr i8, ptr %a, i64 8
51  %8 = getelementptr i8, ptr %b, i64 8
52  %9 = load i8, ptr %7, align 1
53  %10 = load i8, ptr %8, align 1
54  %11 = zext i8 %9 to i32
55  %12 = zext i8 %10 to i32
56  %13 = sub i32 %11, %12
57  br label %endblock
58
59endblock:
60  %phi.res = phi i32 [ %13, %loadbb1 ], [ %1, %res_block ]
61  %icmp = icmp slt i32 %phi.res, 0
62  ret i1 %icmp
63}
64