1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr10 -verify-machineinstrs \ 3; RUN: < %s | FileCheck %s --check-prefix=AIX 4; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr10 -verify-machineinstrs \ 5; RUN: < %s | FileCheck %s --check-prefix=AIX-32 6; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \ 7; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \ 8; RUN: | FileCheck %s --check-prefix=LE 9; RUN: llc -verify-machineinstrs -mtriple powerpcle-unknown-linux-gnu \ 10; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \ 11; RUN: | FileCheck %s --check-prefix=LE-32 12; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu \ 13; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \ 14; RUN: | FileCheck %s --check-prefix=BE 15; RUN: llc -verify-machineinstrs -mtriple powerpc-unknown-linux-gnu \ 16; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \ 17; RUN: | FileCheck %s --check-prefix=BE-32 18 19 20; Function Attrs: nounwind 21define dso_local <4 x i16> @shufflevector_combine(<4 x i32> %0) #0 { 22; AIX-LABEL: shufflevector_combine: 23; AIX: # %bb.0: # %newFuncRoot 24; AIX-NEXT: ld 3, L..C0(2) # %const.0 25; AIX-NEXT: xxlxor 1, 1, 1 26; AIX-NEXT: lxv 0, 0(3) 27; AIX-NEXT: li 3, 0 28; AIX-NEXT: xxperm 34, 1, 0 29; AIX-NEXT: vinsw 2, 3, 8 30; AIX-NEXT: vpkuwum 2, 2, 2 31; AIX-NEXT: blr 32; 33; AIX-32-LABEL: shufflevector_combine: 34; AIX-32: # %bb.0: # %newFuncRoot 35; AIX-32-NEXT: lwz 3, L..C0(2) # %const.0 36; AIX-32-NEXT: xxlxor 1, 1, 1 37; AIX-32-NEXT: lxv 0, 0(3) 38; AIX-32-NEXT: li 3, 0 39; AIX-32-NEXT: xxperm 34, 1, 0 40; AIX-32-NEXT: vinsw 2, 3, 8 41; AIX-32-NEXT: vpkuwum 2, 2, 2 42; AIX-32-NEXT: blr 43; 44; LE-LABEL: shufflevector_combine: 45; LE: # %bb.0: # %newFuncRoot 46; LE-NEXT: plxv vs0, .LCPI0_0@PCREL(0), 1 47; LE-NEXT: xxlxor v3, v3, v3 48; LE-NEXT: li r3, 0 49; LE-NEXT: xxperm v3, v2, vs0 50; LE-NEXT: vinsw v3, r3, 4 51; LE-NEXT: vpkuwum v2, v3, v3 52; LE-NEXT: blr 53; 54; LE-32-LABEL: shufflevector_combine: 55; LE-32: # %bb.0: # %newFuncRoot 56; LE-32-NEXT: li r3, .LCPI0_0@l 57; LE-32-NEXT: lis r4, .LCPI0_0@ha 58; LE-32-NEXT: xxlxor v3, v3, v3 59; LE-32-NEXT: lxvx vs0, r4, r3 60; LE-32-NEXT: li r3, 0 61; LE-32-NEXT: xxperm v3, v2, vs0 62; LE-32-NEXT: vinsw v3, r3, 4 63; LE-32-NEXT: vpkuwum v2, v3, v3 64; LE-32-NEXT: blr 65; 66; BE-LABEL: shufflevector_combine: 67; BE: # %bb.0: # %newFuncRoot 68; BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha 69; BE-NEXT: xxlxor vs1, vs1, vs1 70; BE-NEXT: addi r3, r3, .LCPI0_0@toc@l 71; BE-NEXT: lxv vs0, 0(r3) 72; BE-NEXT: li r3, 0 73; BE-NEXT: xxperm v2, vs1, vs0 74; BE-NEXT: vinsw v2, r3, 8 75; BE-NEXT: vpkuwum v2, v2, v2 76; BE-NEXT: blr 77; 78; BE-32-LABEL: shufflevector_combine: 79; BE-32: # %bb.0: # %newFuncRoot 80; BE-32-NEXT: li r3, .LCPI0_0@l 81; BE-32-NEXT: lis r4, .LCPI0_0@ha 82; BE-32-NEXT: xxlxor vs1, vs1, vs1 83; BE-32-NEXT: lxvx vs0, r4, r3 84; BE-32-NEXT: li r3, 0 85; BE-32-NEXT: xxperm v2, vs1, vs0 86; BE-32-NEXT: vinsw v2, r3, 8 87; BE-32-NEXT: vpkuwum v2, v2, v2 88; BE-32-NEXT: blr 89newFuncRoot: 90 %1 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %0, <4 x i32> <i32 0, i32 7, i32 undef, i32 6> 91 %2 = insertelement <4 x i32> %1, i32 0, i64 2 92 %3 = trunc <4 x i32> %2 to <4 x i16> 93 ret <4 x i16> %3 94} 95 96attributes #0 = { nounwind } 97