1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-vsr-nums-as-vr \ 3; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s 4; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu -ppc-vsr-nums-as-vr \ 5; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=CHECK-BE 6 7@Globi = external global i32, align 4 8@Globf = external global float, align 4 9 10define <2 x i64> @test1(i64 %a, i64 %b) { 11; CHECK-LABEL: test1: 12; CHECK: # %bb.0: # %entry 13; CHECK-NEXT: mtvsrdd v2, r4, r3 14; CHECK-NEXT: blr 15; 16; CHECK-BE-LABEL: test1: 17; CHECK-BE: # %bb.0: # %entry 18; CHECK-BE-NEXT: mtvsrdd v2, r3, r4 19; CHECK-BE-NEXT: blr 20 21entry: 22; The FIXME below is due to the lowering for BUILD_VECTOR needing a re-vamp 23; which will happen in a subsequent patch. 24 %vecins = insertelement <2 x i64> undef, i64 %a, i32 0 25 %vecins1 = insertelement <2 x i64> %vecins, i64 %b, i32 1 26 ret <2 x i64> %vecins1 27} 28 29define i64 @test2(<2 x i64> %a) { 30; CHECK-LABEL: test2: 31; CHECK: # %bb.0: # %entry 32; CHECK-NEXT: mfvsrld r3, v2 33; CHECK-NEXT: blr 34; 35; CHECK-BE-LABEL: test2: 36; CHECK-BE: # %bb.0: # %entry 37; CHECK-BE-NEXT: mfvsrd r3, v2 38; CHECK-BE-NEXT: blr 39 40entry: 41 %0 = extractelement <2 x i64> %a, i32 0 42 ret i64 %0 43} 44 45define i64 @test3(<2 x i64> %a) { 46; CHECK-LABEL: test3: 47; CHECK: # %bb.0: # %entry 48; CHECK-NEXT: mfvsrd r3, v2 49; CHECK-NEXT: blr 50; 51; CHECK-BE-LABEL: test3: 52; CHECK-BE: # %bb.0: # %entry 53; CHECK-BE-NEXT: mfvsrld r3, v2 54; CHECK-BE-NEXT: blr 55 56entry: 57 %0 = extractelement <2 x i64> %a, i32 1 58 ret i64 %0 59} 60 61define <4 x i32> @test4(ptr nocapture readonly %in) { 62; CHECK-LABEL: test4: 63; CHECK: # %bb.0: # %entry 64; CHECK-NEXT: lxvwsx v2, 0, r3 65; CHECK-NEXT: blr 66; 67; CHECK-BE-LABEL: test4: 68; CHECK-BE: # %bb.0: # %entry 69; CHECK-BE-NEXT: lxvwsx v2, 0, r3 70; CHECK-BE-NEXT: blr 71 72entry: 73 %0 = load i32, ptr %in, align 4 74 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 75 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 76 ret <4 x i32> %splat.splat 77} 78 79define <4 x float> @test5(ptr nocapture readonly %in) { 80; CHECK-LABEL: test5: 81; CHECK: # %bb.0: # %entry 82; CHECK-NEXT: lxvwsx v2, 0, r3 83; CHECK-NEXT: blr 84; 85; CHECK-BE-LABEL: test5: 86; CHECK-BE: # %bb.0: # %entry 87; CHECK-BE-NEXT: lxvwsx v2, 0, r3 88; CHECK-BE-NEXT: blr 89 90entry: 91 %0 = load float, ptr %in, align 4 92 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0 93 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer 94 ret <4 x float> %splat.splat 95} 96 97define <4 x i32> @test6() { 98; CHECK-LABEL: test6: 99; CHECK: # %bb.0: # %entry 100; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 101; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 102; CHECK-NEXT: lxvwsx v2, 0, r3 103; CHECK-NEXT: blr 104; 105; CHECK-BE-LABEL: test6: 106; CHECK-BE: # %bb.0: # %entry 107; CHECK-BE-NEXT: addis r3, r2, .LC0@toc@ha 108; CHECK-BE-NEXT: ld r3, .LC0@toc@l(r3) 109; CHECK-BE-NEXT: lxvwsx v2, 0, r3 110; CHECK-BE-NEXT: blr 111 112entry: 113 %0 = load i32, ptr @Globi, align 4 114 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 115 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 116 ret <4 x i32> %splat.splat 117} 118 119define <4 x float> @test7() { 120; CHECK-LABEL: test7: 121; CHECK: # %bb.0: # %entry 122; CHECK-NEXT: addis r3, r2, .LC1@toc@ha 123; CHECK-NEXT: ld r3, .LC1@toc@l(r3) 124; CHECK-NEXT: lxvwsx v2, 0, r3 125; CHECK-NEXT: blr 126; 127; CHECK-BE-LABEL: test7: 128; CHECK-BE: # %bb.0: # %entry 129; CHECK-BE-NEXT: addis r3, r2, .LC1@toc@ha 130; CHECK-BE-NEXT: ld r3, .LC1@toc@l(r3) 131; CHECK-BE-NEXT: lxvwsx v2, 0, r3 132; CHECK-BE-NEXT: blr 133 134entry: 135 %0 = load float, ptr @Globf, align 4 136 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0 137 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer 138 ret <4 x float> %splat.splat 139} 140 141define <16 x i8> @test8() { 142; CHECK-LABEL: test8: 143; CHECK: # %bb.0: # %entry 144; CHECK-NEXT: xxlxor v2, v2, v2 145; CHECK-NEXT: blr 146; 147; CHECK-BE-LABEL: test8: 148; CHECK-BE: # %bb.0: # %entry 149; CHECK-BE-NEXT: xxlxor v2, v2, v2 150; CHECK-BE-NEXT: blr 151 152entry: 153 ret <16 x i8> zeroinitializer 154} 155 156define <16 x i8> @test9() { 157; CHECK-LABEL: test9: 158; CHECK: # %bb.0: # %entry 159; CHECK-NEXT: xxspltib v2, 1 160; CHECK-NEXT: blr 161; 162; CHECK-BE-LABEL: test9: 163; CHECK-BE: # %bb.0: # %entry 164; CHECK-BE-NEXT: xxspltib v2, 1 165; CHECK-BE-NEXT: blr 166 167entry: 168 ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 169} 170 171define <16 x i8> @test10() { 172; CHECK-LABEL: test10: 173; CHECK: # %bb.0: # %entry 174; CHECK-NEXT: xxspltib v2, 127 175; CHECK-NEXT: blr 176; 177; CHECK-BE-LABEL: test10: 178; CHECK-BE: # %bb.0: # %entry 179; CHECK-BE-NEXT: xxspltib v2, 127 180; CHECK-BE-NEXT: blr 181 182entry: 183 ret <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127> 184} 185 186define <16 x i8> @test11() { 187; CHECK-LABEL: test11: 188; CHECK: # %bb.0: # %entry 189; CHECK-NEXT: xxspltib v2, 128 190; CHECK-NEXT: blr 191; 192; CHECK-BE-LABEL: test11: 193; CHECK-BE: # %bb.0: # %entry 194; CHECK-BE-NEXT: xxspltib v2, 128 195; CHECK-BE-NEXT: blr 196 197entry: 198 ret <16 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128> 199} 200 201define <16 x i8> @test12() { 202; CHECK-LABEL: test12: 203; CHECK: # %bb.0: # %entry 204; CHECK-NEXT: xxleqv v2, v2, v2 205; CHECK-NEXT: blr 206; 207; CHECK-BE-LABEL: test12: 208; CHECK-BE: # %bb.0: # %entry 209; CHECK-BE-NEXT: xxleqv v2, v2, v2 210; CHECK-BE-NEXT: blr 211 212entry: 213 ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 214} 215 216define <16 x i8> @test13() { 217; CHECK-LABEL: test13: 218; CHECK: # %bb.0: # %entry 219; CHECK-NEXT: xxspltib v2, 129 220; CHECK-NEXT: blr 221; 222; CHECK-BE-LABEL: test13: 223; CHECK-BE: # %bb.0: # %entry 224; CHECK-BE-NEXT: xxspltib v2, 129 225; CHECK-BE-NEXT: blr 226 227entry: 228 ret <16 x i8> <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127> 229} 230 231define <16 x i8> @test13E127() { 232; CHECK-LABEL: test13E127: 233; CHECK: # %bb.0: # %entry 234; CHECK-NEXT: xxspltib v2, 200 235; CHECK-NEXT: blr 236; 237; CHECK-BE-LABEL: test13E127: 238; CHECK-BE: # %bb.0: # %entry 239; CHECK-BE-NEXT: xxspltib v2, 200 240; CHECK-BE-NEXT: blr 241 242entry: 243 ret <16 x i8> <i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200> 244} 245 246define <4 x i32> @test14(<4 x i32> %a, ptr nocapture readonly %b) { 247; CHECK-LABEL: test14: 248; CHECK: # %bb.0: # %entry 249; CHECK-NEXT: lwz r3, 0(r5) 250; CHECK-NEXT: mtfprwz f0, r3 251; CHECK-NEXT: addi r3, r3, 5 252; CHECK-NEXT: xxspltw v2, vs0, 1 253; CHECK-NEXT: stw r3, 0(r5) 254; CHECK-NEXT: blr 255; 256; CHECK-BE-LABEL: test14: 257; CHECK-BE: # %bb.0: # %entry 258; CHECK-BE-NEXT: lwz r3, 0(r5) 259; CHECK-BE-NEXT: mtfprwz f0, r3 260; CHECK-BE-NEXT: addi r3, r3, 5 261; CHECK-BE-NEXT: xxspltw v2, vs0, 1 262; CHECK-BE-NEXT: stw r3, 0(r5) 263; CHECK-BE-NEXT: blr 264 265entry: 266 %0 = load i32, ptr %b, align 4 267 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 268 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 269 %1 = add i32 %0, 5 270 store i32 %1, ptr %b, align 4 271 ret <4 x i32> %splat.splat 272} 273