xref: /llvm-project/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-afn.ll (revision 8ce13bc93be423d2a368f804ed18edf21b489c2e) 
1; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s
2; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s
3
4declare float @llvm.pow.f32 (float, float);
5declare double @llvm.pow.f64 (double, double);
6
7; afn flag powf with 0.25
8define float @llvmintr_powf_f32_afn025(float %a) {
9; CHECK-LNX-LABEL: llvmintr_powf_f32_afn025:
10; CHECK-LNX:       bl __xl_powf
11; CHECK-LNX:       blr
12;
13; CHECK-AIX-LABEL: llvmintr_powf_f32_afn025:
14; CHECK-AIX:       bl .__xl_powf[PR]
15; CHECK-AIX:       blr
16entry:
17  %call = tail call afn float @llvm.pow.f32(float %a, float 2.500000e-01)
18  ret float %call
19}
20
21; afn flag pow with 0.25
22define double @llvmintr_pow_f64_afn025(double %a) {
23; CHECK-LNX-LABEL: llvmintr_pow_f64_afn025:
24; CHECK-LNX:       bl __xl_pow
25; CHECK-LNX:       blr
26;
27; CHECK-AIX-LABEL: llvmintr_pow_f64_afn025:
28; CHECK-AIX:       bl .__xl_pow[PR]
29; CHECK-AIX:       blr
30entry:
31  %call = tail call afn double @llvm.pow.f64(double %a, double 2.500000e-01)
32  ret double %call
33}
34
35; afn flag powf with 0.75
36define float @llvmintr_powf_f32_afn075(float %a) {
37; CHECK-LNX-LABEL: llvmintr_powf_f32_afn075:
38; CHECK-LNX:       bl __xl_powf
39; CHECK-LNX:       blr
40;
41; CHECK-AIX-LABEL: llvmintr_powf_f32_afn075:
42; CHECK-AIX:       # %bb.0: # %entry
43; CHECK-AIX:       bl .__xl_powf[PR]
44; CHECK-AIX:       blr
45entry:
46  %call = tail call afn float @llvm.pow.f32(float %a, float 7.500000e-01)
47  ret float %call
48}
49
50; afn flag pow with 0.75
51define double @llvmintr_pow_f64_afn075(double %a) {
52; CHECK-LNX-LABEL: llvmintr_pow_f64_afn075:
53; CHECK-LNX:       bl __xl_pow
54; CHECK-LNX:       blr
55;
56; CHECK-AIX-LABEL: llvmintr_pow_f64_afn075:
57; CHECK-AIX:       bl .__xl_pow[PR]
58; CHECK-AIX:       blr
59entry:
60  %call = tail call afn double @llvm.pow.f64(double %a, double 7.500000e-01)
61  ret double %call
62}
63
64; afn flag powf with 0.50
65define float @llvmintr_powf_f32_afn050(float %a) {
66; CHECK-LNX-LABEL: llvmintr_powf_f32_afn050:
67; CHECK-LNX:       # %bb.0: # %entry
68; CHECK-LNX:       bl __xl_powf
69; CHECK-LNX:       blr
70;
71; CHECK-AIX-LABEL: llvmintr_powf_f32_afn050:
72; CHECK-AIX:       # %bb.0: # %entry
73; CHECK-AIX:       bl .__xl_powf[PR]
74; CHECK-AIX:       blr
75entry:
76  %call = tail call afn float @llvm.pow.f32(float %a, float 5.000000e-01)
77  ret float %call
78}
79
80; afn flag pow with 0.50
81define double @llvmintr_pow_f64_afn050(double %a) {
82; CHECK-LNX-LABEL: llvmintr_pow_f64_afn050:
83; CHECK-LNX:       # %bb.0: # %entry
84; CHECK-LNX:       bl __xl_pow
85; CHECK-LNX:       blr
86;
87; CHECK-AIX-LABEL: llvmintr_pow_f64_afn050:
88; CHECK-AIX:       # %bb.0: # %entry
89; CHECK-AIX:       bl .__xl_pow[PR]
90; CHECK-AIX:       blr
91entry:
92  %call = tail call afn double @llvm.pow.f64(double %a, double 5.000000e-01)
93  ret double %call
94}
95