1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple powerpc64 -mcpu=pwr10 < %s | FileCheck %s --check-prefix=BE 3; RUN: llc -mtriple powerpc64le -mcpu=pwr10 < %s | FileCheck %s --check-prefix=LE 4; RUN: llc -mtriple powerpc64le -mcpu=pwr10 -ppc-disable-perfect-shuffle=false < %s | FileCheck %s --check-prefix=LE 5; RUN: llc -mtriple powerpc64 -mcpu=pwr10 -ppc-disable-perfect-shuffle=false < %s | FileCheck %s --check-prefix=BE-ENABLE 6 7; TODO: Fix the worse codegen when disabling perfect shuffle 8 9define <4 x float> @shuffle1(<16 x i8> %v1, <16 x i8> %v2) { 10; BE-LABEL: shuffle1: 11; BE: # %bb.0: 12; BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha 13; BE-NEXT: addi 3, 3, .LCPI0_0@toc@l 14; BE-NEXT: lxv 36, 0(3) 15; BE-NEXT: vperm 2, 2, 3, 4 16; BE-NEXT: blr 17; 18; LE-LABEL: shuffle1: 19; LE: # %bb.0: 20; LE-NEXT: vpkudum 2, 3, 2 21; LE-NEXT: blr 22; 23; BE-ENABLE-LABEL: shuffle1: 24; BE-ENABLE: # %bb.0: 25; BE-ENABLE-NEXT: xxmrglw 0, 34, 35 26; BE-ENABLE-NEXT: xxmrghw 1, 34, 35 27; BE-ENABLE-NEXT: xxmrghw 34, 1, 0 28; BE-ENABLE-NEXT: blr 29 %shuf = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27> 30 %cast = bitcast <16 x i8> %shuf to <4 x float> 31 ret <4 x float> %cast 32} 33 34define <4 x float> @shuffle2(<16 x i8> %v1, <16 x i8> %v2) { 35; BE-LABEL: shuffle2: 36; BE: # %bb.0: 37; BE-NEXT: vpkudum 2, 2, 3 38; BE-NEXT: blr 39; 40; LE-LABEL: shuffle2: 41; LE: # %bb.0: 42; LE-NEXT: plxv 36, .LCPI1_0@PCREL(0), 1 43; LE-NEXT: vperm 2, 3, 2, 4 44; LE-NEXT: blr 45; 46; BE-ENABLE-LABEL: shuffle2: 47; BE-ENABLE: # %bb.0: 48; BE-ENABLE-NEXT: vpkudum 2, 2, 3 49; BE-ENABLE-NEXT: blr 50 %shuf = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31> 51 %cast = bitcast <16 x i8> %shuf to <4 x float> 52 ret <4 x float> %cast 53} 54 55define <4 x float> @shuffle3(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3, <16 x i8> %v4) { 56; BE-LABEL: shuffle3: 57; BE: # %bb.0: 58; BE-NEXT: addis 3, 2, .LCPI2_0@toc@ha 59; BE-NEXT: addi 3, 3, .LCPI2_0@toc@l 60; BE-NEXT: lxv 32, 0(3) 61; BE-NEXT: vperm 2, 2, 3, 0 62; BE-NEXT: vperm 3, 4, 5, 0 63; BE-NEXT: xvaddsp 34, 34, 35 64; BE-NEXT: blr 65; 66; LE-LABEL: shuffle3: 67; LE: # %bb.0: 68; LE-NEXT: vpkudum 2, 3, 2 69; LE-NEXT: vpkudum 3, 5, 4 70; LE-NEXT: xvaddsp 34, 34, 35 71; LE-NEXT: blr 72; 73; BE-ENABLE-LABEL: shuffle3: 74; BE-ENABLE: # %bb.0: 75; BE-ENABLE-NEXT: xxmrglw 0, 34, 35 76; BE-ENABLE-NEXT: xxmrghw 1, 34, 35 77; BE-ENABLE-NEXT: xxmrghw 34, 1, 0 78; BE-ENABLE-NEXT: xxmrglw 0, 36, 37 79; BE-ENABLE-NEXT: xxmrghw 1, 36, 37 80; BE-ENABLE-NEXT: xxmrghw 35, 1, 0 81; BE-ENABLE-NEXT: xvaddsp 34, 34, 35 82; BE-ENABLE-NEXT: blr 83 %shuf1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27> 84 %shuf2 = shufflevector <16 x i8> %v3, <16 x i8> %v4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27> 85 %cast1 = bitcast <16 x i8> %shuf1 to <4 x float> 86 %cast2 = bitcast <16 x i8> %shuf2 to <4 x float> 87 %add = fadd <4 x float> %cast1, %cast2 88 ret <4 x float> %add 89} 90 91define <4 x float> @shuffle4(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3, <16 x i8> %v4) { 92; BE-LABEL: shuffle4: 93; BE: # %bb.0: 94; BE-NEXT: vpkudum 2, 2, 3 95; BE-NEXT: vpkudum 3, 4, 5 96; BE-NEXT: xvaddsp 34, 34, 35 97; BE-NEXT: blr 98; 99; LE-LABEL: shuffle4: 100; LE: # %bb.0: 101; LE-NEXT: plxv 32, .LCPI3_0@PCREL(0), 1 102; LE-NEXT: vperm 2, 3, 2, 0 103; LE-NEXT: vperm 3, 5, 4, 0 104; LE-NEXT: xvaddsp 34, 34, 35 105; LE-NEXT: blr 106; 107; BE-ENABLE-LABEL: shuffle4: 108; BE-ENABLE: # %bb.0: 109; BE-ENABLE-NEXT: vpkudum 2, 2, 3 110; BE-ENABLE-NEXT: vpkudum 3, 4, 5 111; BE-ENABLE-NEXT: xvaddsp 34, 34, 35 112; BE-ENABLE-NEXT: blr 113 %shuf1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31> 114 %shuf2 = shufflevector <16 x i8> %v3, <16 x i8> %v4, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31> 115 %cast1 = bitcast <16 x i8> %shuf1 to <4 x float> 116 %cast2 = bitcast <16 x i8> %shuf2 to <4 x float> 117 %add = fadd <4 x float> %cast1, %cast2 118 ret <4 x float> %add 119} 120 121define <4 x float> @shuffle5(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3, <16 x i8> %v4) { 122; BE-LABEL: shuffle5: 123; BE: # %bb.0: # %entry 124; BE-NEXT: addis 3, 2, .LCPI4_0@toc@ha 125; BE-NEXT: addi 3, 3, .LCPI4_0@toc@l 126; BE-NEXT: lxv 32, 0(3) 127; BE-NEXT: li 3, 8 128; BE-NEXT: vextublx 3, 3, 2 129; BE-NEXT: andi. 3, 3, 255 130; BE-NEXT: vperm 3, 2, 3, 0 131; BE-NEXT: vmr 2, 3 132; BE-NEXT: beq 0, .LBB4_2 133; BE-NEXT: # %bb.1: # %exit 134; BE-NEXT: xvaddsp 34, 35, 34 135; BE-NEXT: blr 136; BE-NEXT: .LBB4_2: # %second 137; BE-NEXT: vperm 2, 4, 5, 0 138; BE-NEXT: xvaddsp 34, 35, 34 139; BE-NEXT: blr 140; 141; LE-LABEL: shuffle5: 142; LE: # %bb.0: # %entry 143; LE-NEXT: vpkudum 3, 3, 2 144; LE-NEXT: li 3, 8 145; LE-NEXT: vextubrx 3, 3, 2 146; LE-NEXT: vmr 2, 3 147; LE-NEXT: andi. 3, 3, 255 148; LE-NEXT: beq 0, .LBB4_2 149; LE-NEXT: # %bb.1: # %exit 150; LE-NEXT: xvaddsp 34, 35, 34 151; LE-NEXT: blr 152; LE-NEXT: .LBB4_2: # %second 153; LE-NEXT: vpkudum 2, 5, 4 154; LE-NEXT: xvaddsp 34, 35, 34 155; LE-NEXT: blr 156; 157; BE-ENABLE-LABEL: shuffle5: 158; BE-ENABLE: # %bb.0: # %entry 159; BE-ENABLE-NEXT: xxmrglw 0, 34, 35 160; BE-ENABLE-NEXT: xxmrghw 1, 34, 35 161; BE-ENABLE-NEXT: li 3, 8 162; BE-ENABLE-NEXT: vextublx 3, 3, 2 163; BE-ENABLE-NEXT: xxmrghw 0, 1, 0 164; BE-ENABLE-NEXT: andi. 3, 3, 255 165; BE-ENABLE-NEXT: xxlor 1, 0, 0 166; BE-ENABLE-NEXT: beq 0, .LBB4_2 167; BE-ENABLE-NEXT: # %bb.1: # %exit 168; BE-ENABLE-NEXT: xvaddsp 34, 0, 1 169; BE-ENABLE-NEXT: blr 170; BE-ENABLE-NEXT: .LBB4_2: # %second 171; BE-ENABLE-NEXT: xxmrglw 1, 36, 37 172; BE-ENABLE-NEXT: xxmrghw 2, 36, 37 173; BE-ENABLE-NEXT: xxmrghw 1, 2, 1 174; BE-ENABLE-NEXT: xvaddsp 34, 0, 1 175; BE-ENABLE-NEXT: blr 176entry: 177 %shuf1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27> 178 %fetch = extractelement <16 x i8> %shuf1, i32 4 179 %icmp = icmp eq i8 %fetch, 0 180 br i1 %icmp, label %second, label %exit 181 182second: 183 %shufs = shufflevector <16 x i8> %v3, <16 x i8> %v4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27> 184 br label %exit 185 186exit: 187 %shuf2 = phi <16 x i8> [%shuf1, %entry], [%shufs, %second] 188 %cast1 = bitcast <16 x i8> %shuf1 to <4 x float> 189 %cast2 = bitcast <16 x i8> %shuf2 to <4 x float> 190 %add = fadd <4 x float> %cast1, %cast2 191 ret <4 x float> %add 192} 193