1# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 %s -o - \ 2# RUN: -run-pass=ppc-mi-peepholes -verify-machineinstrs | FileCheck %s 3 4# Test the peephole replacing unprimed accumulator PHI nodes by primed 5# accumulator PHI nodes. We have a test for the simple case (PHI nodes with COPY 6# operands), a test for PHI nodes with IMPLICIT_DEF operands, a test for PHI 7# nodes with operands being other PHI nodes on unprimed accumulators and a test 8# with an unprimed accumulator PHI node cycle. 9 10--- | 11 define dso_local void @phiCopy(i32 signext %i, <16 x i8> %vc, ptr nocapture %ptr) { 12 entry: 13 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz() 14 %tobool.not = icmp eq i32 %i, 0 15 br i1 %tobool.not, label %if.end, label %if.then 16 17 if.then: 18 %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc) 19 br label %if.end 20 21 if.end: 22 %vq.0 = phi <512 x i1> [ %1, %if.then ], [ %0, %entry ] 23 store <512 x i1> %vq.0, ptr %ptr, align 64 24 ret void 25 } 26 27 declare <512 x i1> @llvm.ppc.mma.xxsetaccz() 28 29 declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>) 30 31 define dso_local void @phiCopyUndef(i32 signext %i, <16 x i8> %vc, ptr nocapture %ptr) { 32 entry: 33 %tobool.not = icmp eq i32 %i, 0 34 br i1 %tobool.not, label %if.end, label %if.then 35 36 if.then: 37 %0 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> undef, <16 x i8> %vc, <16 x i8> %vc) 38 br label %if.end 39 40 if.end: 41 %vq.0 = phi <512 x i1> [ %0, %if.then ], [ undef, %entry ] 42 store <512 x i1> %vq.0, ptr %ptr, align 64 43 ret void 44 } 45 46 define dso_local void @phiPhis(i32 signext %i, <16 x i8> %vc, ptr nocapture %ptr) { 47 entry: 48 %cmp6 = icmp sgt i32 %i, 0 49 br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup 50 51 for.body.preheader: 52 %0 = add i32 %i, -1 53 %xtraiter = and i32 %i, 7 54 %1 = icmp ult i32 %0, 7 55 br i1 %1, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body.preheader.new 56 57 for.body.preheader.new: 58 %unroll_iter = and i32 %i, -8 59 %2 = add i32 %unroll_iter, -8 60 %3 = zext i32 %2 to i64 61 %4 = lshr i64 %3, 3 62 %5 = add nuw nsw i64 %4, 1 63 call void @llvm.set.loop.iterations.i64(i64 %5) 64 br label %for.body 65 66 for.cond.cleanup.loopexit.unr-lcssa: 67 %vq.07.unr = phi <512 x i1> [ undef, %for.body.preheader ], [ %18, %for.body ] 68 %lcmp.mod.not = icmp eq i32 %xtraiter, 0 69 br i1 %lcmp.mod.not, label %for.cond.cleanup, label %for.body.epil.preheader 70 71 for.body.epil.preheader: 72 %6 = add nsw i32 %xtraiter, -1 73 %7 = zext i32 %6 to i64 74 %8 = add nuw nsw i64 %7, 1 75 call void @llvm.set.loop.iterations.i64(i64 %8) 76 br label %for.body.epil 77 78 for.body.epil: 79 %vq.07.epil = phi <512 x i1> [ %9, %for.body.epil ], [ %vq.07.unr, %for.body.epil.preheader ] 80 %9 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %vq.07.epil, <16 x i8> %vc, <16 x i8> %vc) 81 %10 = call i1 @llvm.loop.decrement.i64(i64 1) 82 br i1 %10, label %for.body.epil, label %for.cond.cleanup 83 84 for.cond.cleanup: 85 %vq.0.lcssa = phi <512 x i1> [ undef, %entry ], [ %vq.07.unr, %for.cond.cleanup.loopexit.unr-lcssa ], [ %9, %for.body.epil ] 86 %add.ptr = getelementptr inbounds <512 x i1>, ptr %ptr, i64 1 87 store <512 x i1> %vq.0.lcssa, ptr %add.ptr, align 64 88 ret void 89 90 for.body: 91 %vq.07 = phi <512 x i1> [ undef, %for.body.preheader.new ], [ %18, %for.body ] 92 %11 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %vq.07, <16 x i8> %vc, <16 x i8> %vc) 93 %12 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %11, <16 x i8> %vc, <16 x i8> %vc) 94 %13 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %12, <16 x i8> %vc, <16 x i8> %vc) 95 %14 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %13, <16 x i8> %vc, <16 x i8> %vc) 96 %15 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %14, <16 x i8> %vc, <16 x i8> %vc) 97 %16 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %15, <16 x i8> %vc, <16 x i8> %vc) 98 %17 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %16, <16 x i8> %vc, <16 x i8> %vc) 99 %18 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %17, <16 x i8> %vc, <16 x i8> %vc) 100 %19 = call i1 @llvm.loop.decrement.i64(i64 1) 101 br i1 %19, label %for.body, label %for.cond.cleanup.loopexit.unr-lcssa 102 } 103 104 define dso_local void @phiCycle(i32 signext %i, <16 x i8> %vc, ptr nocapture %ptr) { 105 entry: 106 %cmp6 = icmp sgt i32 %i, 0 107 br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup 108 109 for.body.preheader: 110 %0 = add i32 %i, -1 111 %xtraiter = and i32 %i, 7 112 %1 = icmp ult i32 %0, 7 113 br i1 %1, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body.preheader.new 114 115 for.body.preheader.new: 116 %unroll_iter = and i32 %i, -8 117 %2 = add i32 %unroll_iter, -8 118 %3 = zext i32 %2 to i64 119 %4 = lshr i64 %3, 3 120 %5 = add nuw nsw i64 %4, 1 121 call void @llvm.set.loop.iterations.i64(i64 %5) 122 br label %for.body 123 124 for.cond.cleanup.loopexit.unr-lcssa: 125 %vq.07.unr = phi <512 x i1> [ undef, %for.body.preheader ], [ %18, %for.body ], [ %vq.07.epil, %for.body.epil ] 126 %lcmp.mod.not = icmp eq i32 %xtraiter, 0 127 br i1 %lcmp.mod.not, label %for.cond.cleanup, label %for.body.epil.preheader 128 129 for.body.epil.preheader: 130 %6 = add nsw i32 %xtraiter, -1 131 %7 = zext i32 %6 to i64 132 %8 = add nuw nsw i64 %7, 1 133 call void @llvm.set.loop.iterations.i64(i64 %8) 134 br label %for.body.epil 135 136 for.body.epil: 137 %vq.07.epil = phi <512 x i1> [ %9, %for.body.epil ], [ %vq.07.unr, %for.body.epil.preheader ] 138 %9 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %vq.07.epil, <16 x i8> %vc, <16 x i8> %vc) 139 %10 = call i1 @llvm.loop.decrement.i64(i64 1) 140 %test = icmp ult i32 %0, 7 141 br i1 %test, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body.epil 142 ;br i1 %10, label %for.body.epil, label %for.cond.cleanup 143 144 for.cond.cleanup: 145 %vq.0.lcssa = phi <512 x i1> [ undef, %entry ], [ %vq.07.unr, %for.cond.cleanup.loopexit.unr-lcssa ] 146 %add.ptr = getelementptr inbounds <512 x i1>, ptr %ptr, i64 1 147 store <512 x i1> %vq.0.lcssa, ptr %add.ptr, align 64 148 ret void 149 150 for.body: 151 %vq.07 = phi <512 x i1> [ undef, %for.body.preheader.new ], [ %18, %for.body ] 152 %11 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %vq.07, <16 x i8> %vc, <16 x i8> %vc) 153 %12 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %11, <16 x i8> %vc, <16 x i8> %vc) 154 %13 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %12, <16 x i8> %vc, <16 x i8> %vc) 155 %14 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %13, <16 x i8> %vc, <16 x i8> %vc) 156 %15 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %14, <16 x i8> %vc, <16 x i8> %vc) 157 %16 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %15, <16 x i8> %vc, <16 x i8> %vc) 158 %17 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %16, <16 x i8> %vc, <16 x i8> %vc) 159 %18 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %17, <16 x i8> %vc, <16 x i8> %vc) 160 %19 = call i1 @llvm.loop.decrement.i64(i64 1) 161 br i1 %19, label %for.body, label %for.cond.cleanup.loopexit.unr-lcssa 162 } 163 164 declare void @llvm.set.loop.iterations.i64(i64) 165 166 declare i1 @llvm.loop.decrement.i64(i64) 167 168... 169--- 170name: phiCopy 171alignment: 16 172exposesReturnsTwice: false 173legalized: false 174regBankSelected: false 175selected: false 176failedISel: false 177tracksRegLiveness: true 178hasWinCFI: false 179registers: 180 - { id: 0, class: uaccrc, preferred-register: '' } 181 - { id: 1, class: uaccrc, preferred-register: '' } 182 - { id: 2, class: uaccrc, preferred-register: '' } 183 - { id: 3, class: g8rc, preferred-register: '' } 184 - { id: 4, class: vrrc, preferred-register: '' } 185 - { id: 5, class: g8rc_and_g8rc_nox0, preferred-register: '' } 186 - { id: 6, class: gprc, preferred-register: '' } 187 - { id: 7, class: accrc, preferred-register: '' } 188 - { id: 8, class: crrc, preferred-register: '' } 189 - { id: 9, class: vsrc, preferred-register: '' } 190 - { id: 10, class: accrc, preferred-register: '' } 191 - { id: 11, class: accrc, preferred-register: '' } 192 - { id: 12, class: accrc, preferred-register: '' } 193 - { id: 13, class: accrc, preferred-register: '' } 194 - { id: 14, class: vsrc, preferred-register: '' } 195 - { id: 15, class: vsrprc, preferred-register: '' } 196 - { id: 16, class: vsrprc, preferred-register: '' } 197 - { id: 17, class: vsrc, preferred-register: '' } 198 - { id: 18, class: vsrprc, preferred-register: '' } 199 - { id: 19, class: vsrprc, preferred-register: '' } 200 - { id: 20, class: vsrc, preferred-register: '' } 201 - { id: 21, class: vsrprc, preferred-register: '' } 202 - { id: 22, class: vsrprc, preferred-register: '' } 203 - { id: 23, class: vsrc, preferred-register: '' } 204 - { id: 24, class: vsrprc, preferred-register: '' } 205liveins: 206 - { reg: '$x3', virtual-reg: '%3' } 207 - { reg: '$v2', virtual-reg: '%4' } 208 - { reg: '$x7', virtual-reg: '%5' } 209frameInfo: 210 isFrameAddressTaken: false 211 isReturnAddressTaken: false 212 hasStackMap: false 213 hasPatchPoint: false 214 stackSize: 0 215 offsetAdjustment: 0 216 maxAlignment: 1 217 adjustsStack: false 218 hasCalls: false 219 stackProtector: '' 220 maxCallFrameSize: 4294967295 221 cvBytesOfCalleeSavedRegisters: 0 222 hasOpaqueSPAdjustment: false 223 hasVAStart: false 224 hasMustTailInVarArgFunc: false 225 localFrameSize: 0 226 savePoint: '' 227 restorePoint: '' 228fixedStack: [] 229stack: [] 230callSites: [] 231debugValueSubstitutions: [] 232constants: [] 233machineFunctionInfo: {} 234body: | 235 bb.0.entry: 236 successors: %bb.2(0x30000000), %bb.1(0x50000000) 237 liveins: $x3, $v2, $x7 238 239 %5:g8rc_and_g8rc_nox0 = COPY $x7 240 %4:vrrc = COPY $v2 241 %3:g8rc = COPY $x3 242 %6:gprc = COPY %3.sub_32 243 %7:accrc = XXSETACCZ 244 %0:uaccrc = COPY %7 245 %8:crrc = CMPLWI killed %6, 0 246 BCC 76, killed %8, %bb.2 247 B %bb.1 248 249 bb.1.if.then: 250 successors: %bb.2(0x80000000) 251 252 %9:vsrc = COPY %4 253 %11:accrc = COPY %7 254 %10:accrc = XVF32GERPP %11, %9, %9 255 %1:uaccrc = COPY %10 256 257 bb.2.if.end: 258 ; We check that the PHI node on primed accumulator is inserted after 259 ; the label. 260 ; CHECK-LABEL: name: phiCopy 261 ; CHECK-LABEL: bb.{{[0-9]}}.if.end: 262 ; CHECK-NEXT: :accrc = PHI %7, %bb.0, %10, %bb.1 263 ; CHECK-NEXT: %2:uaccrc = PHI 264 %2:uaccrc = PHI %0, %bb.0, %1, %bb.1 265 %13:accrc = COPY %2 266 %12:accrc = XXMFACC %13 267 %14:vsrc = COPY %12.sub_vsx1 268 %16:vsrprc = IMPLICIT_DEF 269 %15:vsrprc = INSERT_SUBREG %16, killed %14, %subreg.sub_vsx1 270 %17:vsrc = COPY %12.sub_vsx0 271 %18:vsrprc = INSERT_SUBREG %15, killed %17, %subreg.sub_vsx0 272 STXVP killed %18, 32, %5 :: (store (s256) into %ir.ptr + 32) 273 %19:vsrprc = COPY %12.sub_pair1 274 %20:vsrc = COPY %19.sub_vsx1 275 %22:vsrprc = IMPLICIT_DEF 276 %21:vsrprc = INSERT_SUBREG %22, killed %20, %subreg.sub_vsx1 277 %23:vsrc = COPY %19.sub_vsx0 278 %24:vsrprc = INSERT_SUBREG %21, killed %23, %subreg.sub_vsx0 279 STXVP killed %24, 0, %5 :: (store (s256) into %ir.ptr, align 64) 280 BLR8 implicit $lr8, implicit $rm 281 282... 283--- 284name: phiCopyUndef 285alignment: 16 286exposesReturnsTwice: false 287legalized: false 288regBankSelected: false 289selected: false 290failedISel: false 291tracksRegLiveness: true 292hasWinCFI: false 293registers: 294 - { id: 0, class: uaccrc, preferred-register: '' } 295 - { id: 1, class: uaccrc, preferred-register: '' } 296 - { id: 2, class: g8rc, preferred-register: '' } 297 - { id: 3, class: vrrc, preferred-register: '' } 298 - { id: 4, class: g8rc_and_g8rc_nox0, preferred-register: '' } 299 - { id: 5, class: uaccrc, preferred-register: '' } 300 - { id: 6, class: gprc, preferred-register: '' } 301 - { id: 7, class: crrc, preferred-register: '' } 302 - { id: 8, class: vsrc, preferred-register: '' } 303 - { id: 9, class: accrc, preferred-register: '' } 304 - { id: 10, class: uaccrc, preferred-register: '' } 305 - { id: 11, class: accrc, preferred-register: '' } 306 - { id: 12, class: accrc, preferred-register: '' } 307 - { id: 13, class: accrc, preferred-register: '' } 308 - { id: 14, class: vsrc, preferred-register: '' } 309 - { id: 15, class: vsrprc, preferred-register: '' } 310 - { id: 16, class: vsrprc, preferred-register: '' } 311 - { id: 17, class: vsrc, preferred-register: '' } 312 - { id: 18, class: vsrprc, preferred-register: '' } 313 - { id: 19, class: vsrprc, preferred-register: '' } 314 - { id: 20, class: vsrc, preferred-register: '' } 315 - { id: 21, class: vsrprc, preferred-register: '' } 316 - { id: 22, class: vsrprc, preferred-register: '' } 317 - { id: 23, class: vsrc, preferred-register: '' } 318 - { id: 24, class: vsrprc, preferred-register: '' } 319liveins: 320 - { reg: '$x3', virtual-reg: '%2' } 321 - { reg: '$v2', virtual-reg: '%3' } 322 - { reg: '$x7', virtual-reg: '%4' } 323frameInfo: 324 isFrameAddressTaken: false 325 isReturnAddressTaken: false 326 hasStackMap: false 327 hasPatchPoint: false 328 stackSize: 0 329 offsetAdjustment: 0 330 maxAlignment: 1 331 adjustsStack: false 332 hasCalls: false 333 stackProtector: '' 334 maxCallFrameSize: 4294967295 335 cvBytesOfCalleeSavedRegisters: 0 336 hasOpaqueSPAdjustment: false 337 hasVAStart: false 338 hasMustTailInVarArgFunc: false 339 localFrameSize: 0 340 savePoint: '' 341 restorePoint: '' 342fixedStack: [] 343stack: [] 344callSites: [] 345debugValueSubstitutions: [] 346constants: [] 347machineFunctionInfo: {} 348body: | 349 bb.0.entry: 350 successors: %bb.3(0x30000000), %bb.1(0x50000000) 351 liveins: $x3, $v2, $x7 352 353 %4:g8rc_and_g8rc_nox0 = COPY $x7 354 %3:vrrc = COPY $v2 355 %2:g8rc = COPY $x3 356 %6:gprc = COPY %2.sub_32 357 %7:crrc = CMPLWI killed %6, 0 358 BCC 68, killed %7, %bb.1 359 360 bb.3: 361 successors: %bb.2(0x80000000) 362 363 %5:uaccrc = IMPLICIT_DEF 364 B %bb.2 365 366 bb.1.if.then: 367 successors: %bb.2(0x80000000) 368 369 %8:vsrc = COPY %3 370 %10:uaccrc = IMPLICIT_DEF 371 %11:accrc = COPY %10 372 %9:accrc = XVF32GERPP %11, %8, %8 373 %0:uaccrc = COPY %9 374 375 bb.2.if.end: 376 ; We check that the PHI node on primed accumulator is inserted after 377 ; the label. 378 ; CHECK-LABEL: name: phiCopyUndef 379 ; CHECK-LABEL: bb.{{[0-9]}}.if.end: 380 ; CHECK-NEXT: :accrc = PHI 381 ; CHECK-NEXT: %1:uaccrc = PHI 382 %1:uaccrc = PHI %5, %bb.3, %0, %bb.1 383 %13:accrc = COPY %1 384 %12:accrc = XXMFACC %13 385 %14:vsrc = COPY %12.sub_vsx1 386 %16:vsrprc = IMPLICIT_DEF 387 %15:vsrprc = INSERT_SUBREG %16, killed %14, %subreg.sub_vsx1 388 %17:vsrc = COPY %12.sub_vsx0 389 %18:vsrprc = INSERT_SUBREG %15, killed %17, %subreg.sub_vsx0 390 STXVP killed %18, 32, %4 :: (store (s256) into %ir.ptr + 32) 391 %19:vsrprc = COPY %12.sub_pair1 392 %20:vsrc = COPY %19.sub_vsx1 393 %22:vsrprc = IMPLICIT_DEF 394 %21:vsrprc = INSERT_SUBREG %22, killed %20, %subreg.sub_vsx1 395 %23:vsrc = COPY %19.sub_vsx0 396 %24:vsrprc = INSERT_SUBREG %21, killed %23, %subreg.sub_vsx0 397 STXVP killed %24, 0, %4 :: (store (s256) into %ir.ptr, align 64) 398 BLR8 implicit $lr8, implicit $rm 399 400... 401--- 402name: phiPhis 403alignment: 16 404exposesReturnsTwice: false 405legalized: false 406regBankSelected: false 407selected: false 408failedISel: false 409tracksRegLiveness: true 410hasWinCFI: false 411registers: 412 - { id: 0, class: gprc_and_gprc_nor0, preferred-register: '' } 413 - { id: 1, class: uaccrc, preferred-register: '' } 414 - { id: 2, class: uaccrc, preferred-register: '' } 415 - { id: 3, class: uaccrc, preferred-register: '' } 416 - { id: 4, class: uaccrc, preferred-register: '' } 417 - { id: 5, class: uaccrc, preferred-register: '' } 418 - { id: 6, class: uaccrc, preferred-register: '' } 419 - { id: 7, class: g8rc, preferred-register: '' } 420 - { id: 8, class: vrrc, preferred-register: '' } 421 - { id: 9, class: g8rc_and_g8rc_nox0, preferred-register: '' } 422 - { id: 10, class: gprc_and_gprc_nor0, preferred-register: '' } 423 - { id: 11, class: uaccrc, preferred-register: '' } 424 - { id: 12, class: crrc, preferred-register: '' } 425 - { id: 13, class: uaccrc, preferred-register: '' } 426 - { id: 14, class: gprc, preferred-register: '' } 427 - { id: 15, class: crrc, preferred-register: '' } 428 - { id: 16, class: uaccrc, preferred-register: '' } 429 - { id: 17, class: gprc_and_gprc_nor0, preferred-register: '' } 430 - { id: 18, class: gprc, preferred-register: '' } 431 - { id: 19, class: g8rc, preferred-register: '' } 432 - { id: 20, class: g8rc, preferred-register: '' } 433 - { id: 21, class: g8rc_and_g8rc_nox0, preferred-register: '' } 434 - { id: 22, class: g8rc, preferred-register: '' } 435 - { id: 23, class: vsrc, preferred-register: '' } 436 - { id: 24, class: accrc, preferred-register: '' } 437 - { id: 25, class: accrc, preferred-register: '' } 438 - { id: 26, class: accrc, preferred-register: '' } 439 - { id: 27, class: accrc, preferred-register: '' } 440 - { id: 28, class: accrc, preferred-register: '' } 441 - { id: 29, class: accrc, preferred-register: '' } 442 - { id: 30, class: accrc, preferred-register: '' } 443 - { id: 31, class: accrc, preferred-register: '' } 444 - { id: 32, class: accrc, preferred-register: '' } 445 - { id: 33, class: crrc, preferred-register: '' } 446 - { id: 34, class: gprc, preferred-register: '' } 447 - { id: 35, class: g8rc, preferred-register: '' } 448 - { id: 36, class: g8rc, preferred-register: '' } 449 - { id: 37, class: g8rc_and_g8rc_nox0, preferred-register: '' } 450 - { id: 38, class: g8rc, preferred-register: '' } 451 - { id: 39, class: vsrc, preferred-register: '' } 452 - { id: 40, class: accrc, preferred-register: '' } 453 - { id: 41, class: accrc, preferred-register: '' } 454 - { id: 42, class: accrc, preferred-register: '' } 455 - { id: 43, class: accrc, preferred-register: '' } 456 - { id: 44, class: vsrc, preferred-register: '' } 457 - { id: 45, class: vsrprc, preferred-register: '' } 458 - { id: 46, class: vsrprc, preferred-register: '' } 459 - { id: 47, class: vsrc, preferred-register: '' } 460 - { id: 48, class: vsrprc, preferred-register: '' } 461 - { id: 49, class: vsrprc, preferred-register: '' } 462 - { id: 50, class: vsrc, preferred-register: '' } 463 - { id: 51, class: vsrprc, preferred-register: '' } 464 - { id: 52, class: vsrprc, preferred-register: '' } 465 - { id: 53, class: vsrc, preferred-register: '' } 466 - { id: 54, class: vsrprc, preferred-register: '' } 467liveins: 468 - { reg: '$x3', virtual-reg: '%7' } 469 - { reg: '$v2', virtual-reg: '%8' } 470 - { reg: '$x7', virtual-reg: '%9' } 471frameInfo: 472 isFrameAddressTaken: false 473 isReturnAddressTaken: false 474 hasStackMap: false 475 hasPatchPoint: false 476 stackSize: 0 477 offsetAdjustment: 0 478 maxAlignment: 1 479 adjustsStack: false 480 hasCalls: false 481 stackProtector: '' 482 maxCallFrameSize: 4294967295 483 cvBytesOfCalleeSavedRegisters: 0 484 hasOpaqueSPAdjustment: false 485 hasVAStart: false 486 hasMustTailInVarArgFunc: false 487 localFrameSize: 0 488 savePoint: '' 489 restorePoint: '' 490fixedStack: [] 491stack: [] 492callSites: [] 493debugValueSubstitutions: [] 494constants: [] 495machineFunctionInfo: {} 496body: | 497 bb.0.entry: 498 successors: %bb.1(0x50000000), %bb.8(0x30000000) 499 liveins: $x3, $v2, $x7 500 501 %9:g8rc_and_g8rc_nox0 = COPY $x7 502 %8:vrrc = COPY $v2 503 %7:g8rc = COPY $x3 504 %10:gprc_and_gprc_nor0 = COPY %7.sub_32 505 %12:crrc = CMPWI %10, 1 506 BCC 4, killed %12, %bb.1 507 508 bb.8: 509 successors: %bb.6(0x80000000) 510 511 %11:uaccrc = IMPLICIT_DEF 512 B %bb.6 513 514 bb.1.for.body.preheader: 515 successors: %bb.3(0x40000000), %bb.2(0x40000000) 516 517 %14:gprc = ADDI %10, -1 518 %0:gprc_and_gprc_nor0 = RLWINM %10, 0, 29, 31 519 %13:uaccrc = IMPLICIT_DEF 520 %15:crrc = CMPLWI killed %14, 7 521 BCC 12, killed %15, %bb.3 522 B %bb.2 523 524 bb.2.for.body.preheader.new: 525 successors: %bb.7(0x80000000) 526 527 %17:gprc_and_gprc_nor0 = RLWINM %10, 0, 0, 28 528 %18:gprc = ADDI killed %17, -8 529 %20:g8rc = IMPLICIT_DEF 530 %19:g8rc = INSERT_SUBREG %20, killed %18, %subreg.sub_32 531 %21:g8rc_and_g8rc_nox0 = RLWINM8 %19, 29, 3, 31 532 %22:g8rc = nuw nsw ADDI8 killed %21, 1 533 MTCTR8loop killed %22, implicit-def dead $ctr8 534 %16:uaccrc = IMPLICIT_DEF 535 B %bb.7 536 537 bb.3.for.cond.cleanup.loopexit.unr-lcssa: 538 successors: %bb.6(0x30000000), %bb.4(0x50000000) 539 540 %1:uaccrc = PHI %13, %bb.1, %6, %bb.7 541 %33:crrc = CMPLWI %0, 0 542 BCC 76, killed %33, %bb.6 543 B %bb.4 544 545 bb.4.for.body.epil.preheader: 546 successors: %bb.5(0x80000000) 547 548 %34:gprc = nsw ADDI %0, -1 549 %36:g8rc = IMPLICIT_DEF 550 %35:g8rc = INSERT_SUBREG %36, killed %34, %subreg.sub_32 551 %37:g8rc_and_g8rc_nox0 = RLDICL killed %35, 0, 32 552 %38:g8rc = nuw nsw ADDI8 killed %37, 1 553 MTCTR8loop killed %38, implicit-def dead $ctr8 554 555 bb.5.for.body.epil: 556 successors: %bb.5(0x7c000000), %bb.6(0x04000000) 557 ; We check that the PHI node on primed accumulator is inserted after 558 ; the label. 559 ; CHECK-LABEL: name: phiPhis 560 ; CHECK-LABEL: bb.{{[0-9]}}.for.body.epil: 561 ; CHECK-NEXT: successors: %bb.{{[0-9]}}(0x{{[0-9a-f]+}}), %bb.{{[0-9]}}(0x{{[0-9a-f]+}}) 562 ; CHECK-NEXT: {{ }} 563 ; CHECK-NEXT: :accrc = PHI 564 ; CHECK-NEXT: %2:uaccrc = PHI 565 %2:uaccrc = PHI %1, %bb.4, %3, %bb.5 566 %39:vsrc = COPY %8 567 %41:accrc = COPY %2 568 %40:accrc = XVF32GERPP %41, %39, %39 569 %3:uaccrc = COPY %40 570 BDNZ8 %bb.5, implicit-def dead $ctr8, implicit $ctr8 571 B %bb.6 572 573 bb.6.for.cond.cleanup: 574 %4:uaccrc = PHI %11, %bb.8, %1, %bb.3, %3, %bb.5 575 %43:accrc = COPY %4 576 %42:accrc = XXMFACC %43 577 %44:vsrc = COPY %42.sub_vsx1 578 %46:vsrprc = IMPLICIT_DEF 579 %45:vsrprc = INSERT_SUBREG %46, killed %44, %subreg.sub_vsx1 580 %47:vsrc = COPY %42.sub_vsx0 581 %48:vsrprc = INSERT_SUBREG %45, killed %47, %subreg.sub_vsx0 582 STXVP killed %48, 96, %9 :: (store (s256) into %ir.add.ptr + 32) 583 %49:vsrprc = COPY %42.sub_pair1 584 %50:vsrc = COPY %49.sub_vsx1 585 %52:vsrprc = IMPLICIT_DEF 586 %51:vsrprc = INSERT_SUBREG %52, killed %50, %subreg.sub_vsx1 587 %53:vsrc = COPY %49.sub_vsx0 588 %54:vsrprc = INSERT_SUBREG %51, killed %53, %subreg.sub_vsx0 589 STXVP killed %54, 64, %9 :: (store (s256) into %ir.add.ptr, align 64) 590 BLR8 implicit $lr8, implicit $rm 591 592 bb.7.for.body: 593 successors: %bb.7(0x7c000000), %bb.3(0x04000000) 594 595 %5:uaccrc = PHI %16, %bb.2, %6, %bb.7 596 %23:vsrc = COPY %8 597 %25:accrc = COPY %5 598 %24:accrc = XVF32GERPP %25, %23, %23 599 %26:accrc = XVF32GERPP %24, %23, %23 600 %27:accrc = XVF32GERPP %26, %23, %23 601 %28:accrc = XVF32GERPP %27, %23, %23 602 %29:accrc = XVF32GERPP %28, %23, %23 603 %30:accrc = XVF32GERPP %29, %23, %23 604 %31:accrc = XVF32GERPP %30, %23, %23 605 %32:accrc = XVF32GERPP %31, %23, %23 606 %6:uaccrc = COPY %32 607 BDNZ8 %bb.7, implicit-def dead $ctr8, implicit $ctr8 608 B %bb.3 609 610... 611--- 612name: phiCycle 613alignment: 16 614exposesReturnsTwice: false 615legalized: false 616regBankSelected: false 617selected: false 618failedISel: false 619tracksRegLiveness: true 620hasWinCFI: false 621registers: 622 - { id: 0, class: gprc_and_gprc_nor0, preferred-register: '' } 623 - { id: 1, class: uaccrc, preferred-register: '' } 624 - { id: 2, class: uaccrc, preferred-register: '' } 625 - { id: 3, class: uaccrc, preferred-register: '' } 626 - { id: 4, class: uaccrc, preferred-register: '' } 627 - { id: 5, class: uaccrc, preferred-register: '' } 628 - { id: 6, class: uaccrc, preferred-register: '' } 629 - { id: 7, class: g8rc, preferred-register: '' } 630 - { id: 8, class: vrrc, preferred-register: '' } 631 - { id: 9, class: g8rc_and_g8rc_nox0, preferred-register: '' } 632 - { id: 10, class: gprc_and_gprc_nor0, preferred-register: '' } 633 - { id: 11, class: uaccrc, preferred-register: '' } 634 - { id: 12, class: crrc, preferred-register: '' } 635 - { id: 13, class: uaccrc, preferred-register: '' } 636 - { id: 14, class: gprc, preferred-register: '' } 637 - { id: 15, class: crrc, preferred-register: '' } 638 - { id: 16, class: uaccrc, preferred-register: '' } 639 - { id: 17, class: gprc_and_gprc_nor0, preferred-register: '' } 640 - { id: 18, class: gprc, preferred-register: '' } 641 - { id: 19, class: g8rc, preferred-register: '' } 642 - { id: 20, class: g8rc, preferred-register: '' } 643 - { id: 21, class: g8rc_and_g8rc_nox0, preferred-register: '' } 644 - { id: 22, class: g8rc, preferred-register: '' } 645 - { id: 23, class: vsrc, preferred-register: '' } 646 - { id: 24, class: accrc, preferred-register: '' } 647 - { id: 25, class: accrc, preferred-register: '' } 648 - { id: 26, class: accrc, preferred-register: '' } 649 - { id: 27, class: accrc, preferred-register: '' } 650 - { id: 28, class: accrc, preferred-register: '' } 651 - { id: 29, class: accrc, preferred-register: '' } 652 - { id: 30, class: accrc, preferred-register: '' } 653 - { id: 31, class: accrc, preferred-register: '' } 654 - { id: 32, class: accrc, preferred-register: '' } 655 - { id: 33, class: crrc, preferred-register: '' } 656 - { id: 34, class: gprc, preferred-register: '' } 657 - { id: 35, class: g8rc, preferred-register: '' } 658 - { id: 36, class: g8rc, preferred-register: '' } 659 - { id: 37, class: g8rc_and_g8rc_nox0, preferred-register: '' } 660 - { id: 38, class: g8rc, preferred-register: '' } 661 - { id: 39, class: vsrc, preferred-register: '' } 662 - { id: 40, class: accrc, preferred-register: '' } 663 - { id: 41, class: accrc, preferred-register: '' } 664 - { id: 42, class: accrc, preferred-register: '' } 665 - { id: 43, class: accrc, preferred-register: '' } 666 - { id: 44, class: vsrc, preferred-register: '' } 667 - { id: 45, class: vsrprc, preferred-register: '' } 668 - { id: 46, class: vsrprc, preferred-register: '' } 669 - { id: 47, class: vsrc, preferred-register: '' } 670 - { id: 48, class: vsrprc, preferred-register: '' } 671 - { id: 49, class: vsrprc, preferred-register: '' } 672 - { id: 50, class: vsrc, preferred-register: '' } 673 - { id: 51, class: vsrprc, preferred-register: '' } 674 - { id: 52, class: vsrprc, preferred-register: '' } 675 - { id: 53, class: vsrc, preferred-register: '' } 676 - { id: 54, class: vsrprc, preferred-register: '' } 677 - { id: 55, class: crrc, preferred-register: '' } 678liveins: 679 - { reg: '$x3', virtual-reg: '%7' } 680 - { reg: '$v2', virtual-reg: '%8' } 681 - { reg: '$x7', virtual-reg: '%9' } 682frameInfo: 683 isFrameAddressTaken: false 684 isReturnAddressTaken: false 685 hasStackMap: false 686 hasPatchPoint: false 687 stackSize: 0 688 offsetAdjustment: 0 689 maxAlignment: 1 690 adjustsStack: false 691 hasCalls: false 692 stackProtector: '' 693 maxCallFrameSize: 4294967295 694 cvBytesOfCalleeSavedRegisters: 0 695 hasOpaqueSPAdjustment: false 696 hasVAStart: false 697 hasMustTailInVarArgFunc: false 698 localFrameSize: 0 699 savePoint: '' 700 restorePoint: '' 701fixedStack: [] 702stack: [] 703callSites: [] 704debugValueSubstitutions: [] 705constants: [] 706machineFunctionInfo: {} 707body: | 708 bb.0.entry: 709 successors: %bb.1(0x50000000), %bb.8(0x30000000) 710 liveins: $x3, $v2, $x7 711 712 %9:g8rc_and_g8rc_nox0 = COPY $x7 713 %8:vrrc = COPY $v2 714 %7:g8rc = COPY $x3 715 %10:gprc_and_gprc_nor0 = COPY %7.sub_32 716 %12:crrc = CMPWI %10, 1 717 BCC 4, killed %12, %bb.1 718 719 bb.8: 720 successors: %bb.6(0x80000000) 721 722 %11:uaccrc = IMPLICIT_DEF 723 B %bb.6 724 725 bb.1.for.body.preheader: 726 successors: %bb.3(0x40000000), %bb.2(0x40000000) 727 728 %14:gprc = ADDI %10, -1 729 %0:gprc_and_gprc_nor0 = RLWINM %10, 0, 29, 31 730 %13:uaccrc = IMPLICIT_DEF 731 %15:crrc = CMPLWI %14, 7 732 BCC 12, killed %15, %bb.3 733 B %bb.2 734 735 bb.2.for.body.preheader.new: 736 successors: %bb.7(0x80000000) 737 738 %17:gprc_and_gprc_nor0 = RLWINM %10, 0, 0, 28 739 %18:gprc = ADDI killed %17, -8 740 %20:g8rc = IMPLICIT_DEF 741 %19:g8rc = INSERT_SUBREG %20, killed %18, %subreg.sub_32 742 %21:g8rc_and_g8rc_nox0 = RLWINM8 %19, 29, 3, 31 743 %22:g8rc = nuw nsw ADDI8 killed %21, 1 744 MTCTR8loop killed %22, implicit-def dead $ctr8 745 %16:uaccrc = IMPLICIT_DEF 746 B %bb.7 747 748 bb.3.for.cond.cleanup.loopexit.unr-lcssa: 749 successors: %bb.6(0x30000000), %bb.4(0x50000000) 750 ; We check that no phi node is inserted in the block. 751 ; CHECK-LABEL: name: phiCycle 752 ; CHECK-LABEL: bb.{{[0-9]}}.for.cond.cleanup.loopexit.unr-lcssa: 753 ; CHECK-NEXT: successors: %bb.{{[0-9]}}(0x{{[0-9a-f]+}}), %bb.{{[0-9]}}(0x{{[0-9a-f]+}}) 754 ; CHECK-NEXT: {{ }} 755 ; CHECK-NEXT: %1:uaccrc = PHI 756 ; CHECK-NEXT: %33:crrc 757 %1:uaccrc = PHI %13, %bb.1, %6, %bb.7, %2, %bb.5 758 %33:crrc = CMPLWI %0, 0 759 BCC 76, killed %33, %bb.6 760 B %bb.4 761 762 bb.4.for.body.epil.preheader: 763 successors: %bb.5(0x80000000) 764 765 %34:gprc = nsw ADDI %0, -1 766 %36:g8rc = IMPLICIT_DEF 767 %35:g8rc = INSERT_SUBREG %36, killed %34, %subreg.sub_32 768 %37:g8rc_and_g8rc_nox0 = RLDICL killed %35, 0, 32 769 %38:g8rc = nuw nsw ADDI8 killed %37, 1 770 MTCTR8loop killed %38, implicit-def dead $ctr8 771 B %bb.5 772 773 bb.5.for.body.epil: 774 successors: %bb.3(0x40000000), %bb.5(0x7c000000) 775 ; We check that no [u]acc phi node is inserted in the block. 776 ; CHECK-LABEL: bb.{{[0-9]}}.for.body.epil: 777 ; CHECK-NEXT: successors: %bb.{{[0-9]}}(0x{{[0-9a-f]+}}), %bb.{{[0-9]}}(0x{{[0-9a-f]+}}) 778 ; CHECK-NOT: uaccrc = PHI 779 ; CHECK-NOT: accrc = PHI 780 ; CHECK: %2:uaccrc = PHI 781 ; CHECK-NEXT: %39:vsrc 782 %2:uaccrc = PHI %1, %bb.4, %3, %bb.5 783 %39:vsrc = COPY %8 784 %41:accrc = COPY %2 785 %40:accrc = XVF32GERPP %41, %39, %39 786 %3:uaccrc = COPY %40 787 %55:crrc = CMPLWI %14, 7 788 BCC 12, killed %55, %bb.5 789 B %bb.3 790 791 bb.6.for.cond.cleanup: 792 %4:uaccrc = PHI %11, %bb.8, %1, %bb.3 793 %43:accrc = COPY %4 794 %42:accrc = XXMFACC %43 795 %44:vsrc = COPY %42.sub_vsx1 796 %46:vsrprc = IMPLICIT_DEF 797 %45:vsrprc = INSERT_SUBREG %46, killed %44, %subreg.sub_vsx1 798 %47:vsrc = COPY %42.sub_vsx0 799 %48:vsrprc = INSERT_SUBREG %45, killed %47, %subreg.sub_vsx0 800 STXVP killed %48, 96, %9 :: (store (s256) into %ir.add.ptr + 32) 801 %49:vsrprc = COPY %42.sub_pair1 802 %50:vsrc = COPY %49.sub_vsx1 803 %52:vsrprc = IMPLICIT_DEF 804 %51:vsrprc = INSERT_SUBREG %52, killed %50, %subreg.sub_vsx1 805 %53:vsrc = COPY %49.sub_vsx0 806 %54:vsrprc = INSERT_SUBREG %51, killed %53, %subreg.sub_vsx0 807 STXVP killed %54, 64, %9 :: (store (s256) into %ir.add.ptr, align 64) 808 BLR8 implicit $lr8, implicit $rm 809 810 bb.7.for.body: 811 successors: %bb.7(0x7c000000), %bb.3(0x04000000) 812 813 %5:uaccrc = PHI %16, %bb.2, %6, %bb.7 814 %23:vsrc = COPY %8 815 %25:accrc = COPY %5 816 %24:accrc = XVF32GERPP %25, %23, %23 817 %26:accrc = XVF32GERPP %24, %23, %23 818 %27:accrc = XVF32GERPP %26, %23, %23 819 %28:accrc = XVF32GERPP %27, %23, %23 820 %29:accrc = XVF32GERPP %28, %23, %23 821 %30:accrc = XVF32GERPP %29, %23, %23 822 %31:accrc = XVF32GERPP %30, %23, %23 823 %32:accrc = XVF32GERPP %31, %23, %23 824 %6:uaccrc = COPY %32 825 BDNZ8 %bb.7, implicit-def dead $ctr8, implicit $ctr8 826 B %bb.3 827 828... 829