xref: /llvm-project/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll (revision 0ad57bf236df9be06811e52c85d4a8ff5f89d387)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
3; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
4; RUN:   < %s | FileCheck %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
6; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
7; RUN:   < %s | FileCheck %s --check-prefix=CHECK-NOMMA
8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
9; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
10; RUN:   < %s | FileCheck %s --check-prefix=CHECK-BE
11; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
12; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
13; RUN:   < %s | FileCheck %s --check-prefix=CHECK-BE-NOMMA
14
15; This test also checks that the paired vector intrinsics are available even
16; when MMA is disabled.
17
18; assemble_pair
19declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
20define void @ass_pair(ptr %ptr, <16 x i8> %vc) {
21; CHECK-LABEL: ass_pair:
22; CHECK:       # %bb.0: # %entry
23; CHECK-NEXT:    stxv v2, 0(r3)
24; CHECK-NEXT:    stxv v2, 16(r3)
25; CHECK-NEXT:    blr
26;
27; CHECK-NOMMA-LABEL: ass_pair:
28; CHECK-NOMMA:       # %bb.0: # %entry
29; CHECK-NOMMA-NEXT:    stxv v2, 0(r3)
30; CHECK-NOMMA-NEXT:    stxv v2, 16(r3)
31; CHECK-NOMMA-NEXT:    blr
32;
33; CHECK-BE-LABEL: ass_pair:
34; CHECK-BE:       # %bb.0: # %entry
35; CHECK-BE-NEXT:    stxv v2, 16(r3)
36; CHECK-BE-NEXT:    stxv v2, 0(r3)
37; CHECK-BE-NEXT:    blr
38;
39; CHECK-BE-NOMMA-LABEL: ass_pair:
40; CHECK-BE-NOMMA:       # %bb.0: # %entry
41; CHECK-BE-NOMMA-NEXT:    stxv v2, 16(r3)
42; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r3)
43; CHECK-BE-NOMMA-NEXT:    blr
44entry:
45  %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
46  store <256 x i1> %0, ptr %ptr, align 32
47  ret void
48}
49
50; disassemble_pair
51declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
52define void @disass_pair(ptr %ptr1, ptr %ptr2, ptr %ptr3) {
53; CHECK-LABEL: disass_pair:
54; CHECK:       # %bb.0: # %entry
55; CHECK-NEXT:    lxv v3, 0(r3)
56; CHECK-NEXT:    lxv v2, 16(r3)
57; CHECK-NEXT:    stxv v3, 0(r4)
58; CHECK-NEXT:    stxv v2, 0(r5)
59; CHECK-NEXT:    blr
60;
61; CHECK-NOMMA-LABEL: disass_pair:
62; CHECK-NOMMA:       # %bb.0: # %entry
63; CHECK-NOMMA-NEXT:    lxv v3, 0(r3)
64; CHECK-NOMMA-NEXT:    lxv v2, 16(r3)
65; CHECK-NOMMA-NEXT:    stxv v3, 0(r4)
66; CHECK-NOMMA-NEXT:    stxv v2, 0(r5)
67; CHECK-NOMMA-NEXT:    blr
68;
69; CHECK-BE-LABEL: disass_pair:
70; CHECK-BE:       # %bb.0: # %entry
71; CHECK-BE-NEXT:    lxv v3, 16(r3)
72; CHECK-BE-NEXT:    lxv v2, 0(r3)
73; CHECK-BE-NEXT:    stxv v2, 0(r4)
74; CHECK-BE-NEXT:    stxv v3, 0(r5)
75; CHECK-BE-NEXT:    blr
76;
77; CHECK-BE-NOMMA-LABEL: disass_pair:
78; CHECK-BE-NOMMA:       # %bb.0: # %entry
79; CHECK-BE-NOMMA-NEXT:    lxv v3, 16(r3)
80; CHECK-BE-NOMMA-NEXT:    lxv v2, 0(r3)
81; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r4)
82; CHECK-BE-NOMMA-NEXT:    stxv v3, 0(r5)
83; CHECK-BE-NOMMA-NEXT:    blr
84entry:
85  %0 = load <256 x i1>, ptr %ptr1, align 32
86  %1 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %0)
87  %2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0
88  %3 = extractvalue { <16 x i8>, <16 x i8> } %1, 1
89  store <16 x i8> %2, ptr %ptr2, align 16
90  store <16 x i8> %3, ptr %ptr3, align 16
91  ret void
92}
93
94define void @test_ldst_1(ptr %vpp, ptr %vp2) {
95; CHECK-LABEL: test_ldst_1:
96; CHECK:       # %bb.0: # %entry
97; CHECK-NEXT:    lxvp vsp34, 0(r3)
98; CHECK-NEXT:    stxvp vsp34, 0(r4)
99; CHECK-NEXT:    blr
100;
101; CHECK-NOMMA-LABEL: test_ldst_1:
102; CHECK-NOMMA:       # %bb.0: # %entry
103; CHECK-NOMMA-NEXT:    lxvp vsp34, 0(r3)
104; CHECK-NOMMA-NEXT:    stxvp vsp34, 0(r4)
105; CHECK-NOMMA-NEXT:    blr
106;
107; CHECK-BE-LABEL: test_ldst_1:
108; CHECK-BE:       # %bb.0: # %entry
109; CHECK-BE-NEXT:    lxvp vsp34, 0(r3)
110; CHECK-BE-NEXT:    stxvp vsp34, 0(r4)
111; CHECK-BE-NEXT:    blr
112;
113; CHECK-BE-NOMMA-LABEL: test_ldst_1:
114; CHECK-BE-NOMMA:       # %bb.0: # %entry
115; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 0(r3)
116; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 0(r4)
117; CHECK-BE-NOMMA-NEXT:    blr
118entry:
119  %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %vpp)
120  tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %0, ptr %vp2)
121  ret void
122}
123
124declare <256 x i1> @llvm.ppc.vsx.lxvp(ptr)
125declare void @llvm.ppc.vsx.stxvp(<256 x i1>, ptr)
126
127define void @test_ldst_2(ptr %vpp, i64 %offset, ptr %vp2)  {
128; CHECK-LABEL: test_ldst_2:
129; CHECK:       # %bb.0: # %entry
130; CHECK-NEXT:    lxvpx vsp34, r3, r4
131; CHECK-NEXT:    stxvpx vsp34, r5, r4
132; CHECK-NEXT:    blr
133;
134; CHECK-NOMMA-LABEL: test_ldst_2:
135; CHECK-NOMMA:       # %bb.0: # %entry
136; CHECK-NOMMA-NEXT:    lxvpx vsp34, r3, r4
137; CHECK-NOMMA-NEXT:    stxvpx vsp34, r5, r4
138; CHECK-NOMMA-NEXT:    blr
139;
140; CHECK-BE-LABEL: test_ldst_2:
141; CHECK-BE:       # %bb.0: # %entry
142; CHECK-BE-NEXT:    lxvpx vsp34, r3, r4
143; CHECK-BE-NEXT:    stxvpx vsp34, r5, r4
144; CHECK-BE-NEXT:    blr
145;
146; CHECK-BE-NOMMA-LABEL: test_ldst_2:
147; CHECK-BE-NOMMA:       # %bb.0: # %entry
148; CHECK-BE-NOMMA-NEXT:    lxvpx vsp34, r3, r4
149; CHECK-BE-NOMMA-NEXT:    stxvpx vsp34, r5, r4
150; CHECK-BE-NOMMA-NEXT:    blr
151entry:
152  %0 = getelementptr i8, ptr %vpp, i64 %offset
153  %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %0)
154  %2 = getelementptr i8, ptr %vp2, i64 %offset
155  tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, ptr %2)
156  ret void
157}
158
159define void @test_ldst_3(ptr %vpp, ptr %vp2)  {
160; CHECK-LABEL: test_ldst_3:
161; CHECK:       # %bb.0: # %entry
162; CHECK-NEXT:    plxvp vsp34, 18(r3), 0
163; CHECK-NEXT:    pstxvp vsp34, 18(r4), 0
164; CHECK-NEXT:    blr
165;
166; CHECK-NOMMA-LABEL: test_ldst_3:
167; CHECK-NOMMA:       # %bb.0: # %entry
168; CHECK-NOMMA-NEXT:    plxvp vsp34, 18(r3), 0
169; CHECK-NOMMA-NEXT:    pstxvp vsp34, 18(r4), 0
170; CHECK-NOMMA-NEXT:    blr
171;
172; CHECK-BE-LABEL: test_ldst_3:
173; CHECK-BE:       # %bb.0: # %entry
174; CHECK-BE-NEXT:    plxvp vsp34, 18(r3), 0
175; CHECK-BE-NEXT:    pstxvp vsp34, 18(r4), 0
176; CHECK-BE-NEXT:    blr
177;
178; CHECK-BE-NOMMA-LABEL: test_ldst_3:
179; CHECK-BE-NOMMA:       # %bb.0: # %entry
180; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 18(r3), 0
181; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 18(r4), 0
182; CHECK-BE-NOMMA-NEXT:    blr
183entry:
184  %0 = getelementptr i8, ptr %vpp, i64 18
185  %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %0)
186  %2 = getelementptr i8, ptr %vp2, i64 18
187  tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, ptr %2)
188  ret void
189}
190
191define void @test_ldst_4(ptr %vpp, ptr %vp2)  {
192; CHECK-LABEL: test_ldst_4:
193; CHECK:       # %bb.0: # %entry
194; CHECK-NEXT:    plxvp vsp34, 1(r3), 0
195; CHECK-NEXT:    pstxvp vsp34, 1(r4), 0
196; CHECK-NEXT:    blr
197;
198; CHECK-NOMMA-LABEL: test_ldst_4:
199; CHECK-NOMMA:       # %bb.0: # %entry
200; CHECK-NOMMA-NEXT:    plxvp vsp34, 1(r3), 0
201; CHECK-NOMMA-NEXT:    pstxvp vsp34, 1(r4), 0
202; CHECK-NOMMA-NEXT:    blr
203;
204; CHECK-BE-LABEL: test_ldst_4:
205; CHECK-BE:       # %bb.0: # %entry
206; CHECK-BE-NEXT:    plxvp vsp34, 1(r3), 0
207; CHECK-BE-NEXT:    pstxvp vsp34, 1(r4), 0
208; CHECK-BE-NEXT:    blr
209;
210; CHECK-BE-NOMMA-LABEL: test_ldst_4:
211; CHECK-BE-NOMMA:       # %bb.0: # %entry
212; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 1(r3), 0
213; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 1(r4), 0
214; CHECK-BE-NOMMA-NEXT:    blr
215entry:
216  %0 = getelementptr i8, ptr %vpp, i64 1
217  %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %0)
218  %2 = getelementptr i8, ptr %vp2, i64 1
219  tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, ptr %2)
220  ret void
221}
222
223define void @test_ldst_5(ptr %vpp, ptr %vp2)  {
224; CHECK-LABEL: test_ldst_5:
225; CHECK:       # %bb.0: # %entry
226; CHECK-NEXT:    plxvp vsp34, 42(r3), 0
227; CHECK-NEXT:    pstxvp vsp34, 42(r4), 0
228; CHECK-NEXT:    blr
229;
230; CHECK-NOMMA-LABEL: test_ldst_5:
231; CHECK-NOMMA:       # %bb.0: # %entry
232; CHECK-NOMMA-NEXT:    plxvp vsp34, 42(r3), 0
233; CHECK-NOMMA-NEXT:    pstxvp vsp34, 42(r4), 0
234; CHECK-NOMMA-NEXT:    blr
235;
236; CHECK-BE-LABEL: test_ldst_5:
237; CHECK-BE:       # %bb.0: # %entry
238; CHECK-BE-NEXT:    plxvp vsp34, 42(r3), 0
239; CHECK-BE-NEXT:    pstxvp vsp34, 42(r4), 0
240; CHECK-BE-NEXT:    blr
241;
242; CHECK-BE-NOMMA-LABEL: test_ldst_5:
243; CHECK-BE-NOMMA:       # %bb.0: # %entry
244; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 42(r3), 0
245; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 42(r4), 0
246; CHECK-BE-NOMMA-NEXT:    blr
247entry:
248  %0 = getelementptr i8, ptr %vpp, i64 42
249  %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %0)
250  %2 = getelementptr i8, ptr %vp2, i64 42
251  tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, ptr %2)
252  ret void
253}
254
255define void @test_ldst_6(ptr %vpp, ptr %vp2)  {
256; CHECK-LABEL: test_ldst_6:
257; CHECK:       # %bb.0: # %entry
258; CHECK-NEXT:    lxvp vsp34, 4096(r3)
259; CHECK-NEXT:    stxvp vsp34, 4096(r4)
260; CHECK-NEXT:    blr
261;
262; CHECK-NOMMA-LABEL: test_ldst_6:
263; CHECK-NOMMA:       # %bb.0: # %entry
264; CHECK-NOMMA-NEXT:    lxvp vsp34, 4096(r3)
265; CHECK-NOMMA-NEXT:    stxvp vsp34, 4096(r4)
266; CHECK-NOMMA-NEXT:    blr
267;
268; CHECK-BE-LABEL: test_ldst_6:
269; CHECK-BE:       # %bb.0: # %entry
270; CHECK-BE-NEXT:    lxvp vsp34, 4096(r3)
271; CHECK-BE-NEXT:    stxvp vsp34, 4096(r4)
272; CHECK-BE-NEXT:    blr
273;
274; CHECK-BE-NOMMA-LABEL: test_ldst_6:
275; CHECK-BE-NOMMA:       # %bb.0: # %entry
276; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 4096(r3)
277; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 4096(r4)
278; CHECK-BE-NOMMA-NEXT:    blr
279entry:
280  %0 = getelementptr <256 x i1>, ptr %vpp, i64 128
281  %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %0)
282  %2 = getelementptr <256 x i1>, ptr %vp2, i64 128
283  tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, ptr %2)
284  ret void
285}
286
287define void @test_ldst_7(ptr %vpp, ptr %vp2)  {
288; FIXME: A prefixed load (plxvp) is expected here as the offset in this
289; test case is a constant that fits within 34-bits.
290; CHECK-LABEL: test_ldst_7:
291; CHECK:       # %bb.0: # %entry
292; CHECK-NEXT:    plxvp vsp34, 32799(r3), 0
293; CHECK-NEXT:    pstxvp vsp34, 32799(r4), 0
294; CHECK-NEXT:    blr
295;
296; CHECK-NOMMA-LABEL: test_ldst_7:
297; CHECK-NOMMA:       # %bb.0: # %entry
298; CHECK-NOMMA-NEXT:    plxvp vsp34, 32799(r3), 0
299; CHECK-NOMMA-NEXT:    pstxvp vsp34, 32799(r4), 0
300; CHECK-NOMMA-NEXT:    blr
301;
302; CHECK-BE-LABEL: test_ldst_7:
303; CHECK-BE:       # %bb.0: # %entry
304; CHECK-BE-NEXT:    plxvp vsp34, 32799(r3), 0
305; CHECK-BE-NEXT:    pstxvp vsp34, 32799(r4), 0
306; CHECK-BE-NEXT:    blr
307;
308; CHECK-BE-NOMMA-LABEL: test_ldst_7:
309; CHECK-BE-NOMMA:       # %bb.0: # %entry
310; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 32799(r3), 0
311; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 32799(r4), 0
312; CHECK-BE-NOMMA-NEXT:    blr
313entry:
314  %0 = getelementptr i8, ptr %vpp, i64 32799
315  %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %0)
316  %2 = getelementptr i8, ptr %vp2, i64 32799
317  tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, ptr %2)
318  ret void
319}
320