xref: /llvm-project/llvm/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll (revision 2a57a08829e8079b59c95ad14f71a1417006c9b5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -verify-machineinstrs -ppc-disable-perfect-shuffle=false < %s | FileCheck %s
3
4; TODO: Fix this case when disabling perfect shuffle
5
6target datalayout = "E-m:e-i64:64-n32:64"
7target triple = "powerpc64-unknown-linux-gnu"
8
9; Function Attrs: nounwind
10define <2 x i32> @test1(<4 x i32> %wide.vec) #0 {
11; CHECK-LABEL: test1:
12; CHECK:       # %bb.0: # %entry
13; CHECK-NEXT:    xxswapd 0, 34
14; CHECK-NEXT:    xxmrghw 34, 34, 0
15; CHECK-NEXT:    blr
16entry:
17  %strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
18  ret <2 x i32> %strided.vec
19}
20
21; Function Attrs: nounwind
22define <16 x i8> @test2(<16 x i8> %wide.vec) #0 {
23; CHECK-LABEL: test2:
24; CHECK:       # %bb.0: # %entry
25; CHECK-NEXT:    xxsldwi 34, 34, 34, 3
26; CHECK-NEXT:    blr
27entry:
28  %strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 10, i32 11>
29  ret <16 x i8> %strided.vec
30}
31
32attributes #0 = { nounwind "target-cpu"="pwr7" }
33
34