1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 6; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 7; RUN: FileCheck %s 8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \ 9; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 10; RUN: FileCheck %s 11 12; This test case aims to test the vector modulo instructions on Power10. 13; The vector modulo instructions operate on signed and unsigned words 14; and doublewords. 15 16; The vector modulo instructions operate on signed and unsigned words, 17; doublewords and 128-bit values. 18 19 20define <1 x i128> @test_vmodsq(<1 x i128> %x, <1 x i128> %y) nounwind readnone { 21; CHECK-LABEL: test_vmodsq: 22; CHECK: # %bb.0: 23; CHECK-NEXT: vmodsq v2, v2, v3 24; CHECK-NEXT: blr 25 %tmp = srem <1 x i128> %x, %y 26 ret <1 x i128> %tmp 27} 28 29define <1 x i128> @test_vmoduq(<1 x i128> %x, <1 x i128> %y) nounwind readnone { 30; CHECK-LABEL: test_vmoduq: 31; CHECK: # %bb.0: 32; CHECK-NEXT: vmoduq v2, v2, v3 33; CHECK-NEXT: blr 34 %tmp = urem <1 x i128> %x, %y 35 ret <1 x i128> %tmp 36} 37 38define <2 x i64> @test_vmodud(<2 x i64> %a, <2 x i64> %b) { 39; CHECK-LABEL: test_vmodud: 40; CHECK: # %bb.0: # %entry 41; CHECK-NEXT: vmodud v2, v2, v3 42; CHECK-NEXT: blr 43entry: 44 %rem = urem <2 x i64> %a, %b 45 ret <2 x i64> %rem 46} 47 48define <2 x i64> @test_vmodsd(<2 x i64> %a, <2 x i64> %b) { 49; CHECK-LABEL: test_vmodsd: 50; CHECK: # %bb.0: # %entry 51; CHECK-NEXT: vmodsd v2, v2, v3 52; CHECK-NEXT: blr 53entry: 54 %rem = srem <2 x i64> %a, %b 55 ret <2 x i64> %rem 56} 57 58define <4 x i32> @test_vmoduw(<4 x i32> %a, <4 x i32> %b) { 59; CHECK-LABEL: test_vmoduw: 60; CHECK: # %bb.0: # %entry 61; CHECK-NEXT: vmoduw v2, v2, v3 62; CHECK-NEXT: blr 63entry: 64 %rem = urem <4 x i32> %a, %b 65 ret <4 x i32> %rem 66} 67 68define <4 x i32> @test_vmodsw(<4 x i32> %a, <4 x i32> %b) { 69; CHECK-LABEL: test_vmodsw: 70; CHECK: # %bb.0: # %entry 71; CHECK-NEXT: vmodsw v2, v2, v3 72; CHECK-NEXT: blr 73entry: 74 %rem = srem <4 x i32> %a, %b 75 ret <4 x i32> %rem 76} 77 78define <2 x i64> @test_vmodud_with_div(<2 x i64> %a, <2 x i64> %b) { 79; CHECK-LABEL: test_vmodud_with_div: 80; CHECK: # %bb.0: # %entry 81; CHECK-NEXT: vmodud v4, v2, v3 82; CHECK-NEXT: vdivud v2, v2, v3 83; CHECK-NEXT: vaddudm v2, v4, v2 84; CHECK-NEXT: blr 85entry: 86 %rem = urem <2 x i64> %a, %b 87 %div = udiv <2 x i64> %a, %b 88 %add = add <2 x i64> %rem, %div 89 ret <2 x i64> %add 90} 91 92define <2 x i64> @test_vmodsd_with_div(<2 x i64> %a, <2 x i64> %b) { 93; CHECK-LABEL: test_vmodsd_with_div: 94; CHECK: # %bb.0: # %entry 95; CHECK-NEXT: vmodsd v4, v2, v3 96; CHECK-NEXT: vdivsd v2, v2, v3 97; CHECK-NEXT: vaddudm v2, v4, v2 98; CHECK-NEXT: blr 99entry: 100 %rem = srem <2 x i64> %a, %b 101 %div = sdiv <2 x i64> %a, %b 102 %add = add <2 x i64> %rem, %div 103 ret <2 x i64> %add 104} 105 106define <4 x i32> @test_vmoduw_with_div(<4 x i32> %a, <4 x i32> %b) { 107; CHECK-LABEL: test_vmoduw_with_div: 108; CHECK: # %bb.0: # %entry 109; CHECK-NEXT: vmoduw v4, v2, v3 110; CHECK-NEXT: vdivuw v2, v2, v3 111; CHECK-NEXT: vadduwm v2, v4, v2 112; CHECK-NEXT: blr 113entry: 114 %rem = urem <4 x i32> %a, %b 115 %div = udiv <4 x i32> %a, %b 116 %add = add <4 x i32> %rem, %div 117 ret <4 x i32> %add 118} 119 120define <4 x i32> @test_vmodsw_div(<4 x i32> %a, <4 x i32> %b) { 121; CHECK-LABEL: test_vmodsw_div: 122; CHECK: # %bb.0: # %entry 123; CHECK-NEXT: vmodsw v4, v2, v3 124; CHECK-NEXT: vdivsw v2, v2, v3 125; CHECK-NEXT: vadduwm v2, v4, v2 126; CHECK-NEXT: blr 127entry: 128 %rem = srem <4 x i32> %a, %b 129 %div = sdiv <4 x i32> %a, %b 130 %add = add <4 x i32> %rem, %div 131 ret <4 x i32> %add 132} 133