1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 6; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 7; RUN: FileCheck %s 8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \ 9; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 10; RUN: FileCheck %s 11 12; This test case aims to test the vector mask manipulation operations 13; on Power10. 14 15declare i32 @llvm.ppc.altivec.vextractbm(<16 x i8>) 16declare i32 @llvm.ppc.altivec.vextracthm(<8 x i16>) 17declare i32 @llvm.ppc.altivec.vextractwm(<4 x i32>) 18declare i32 @llvm.ppc.altivec.vextractdm(<2 x i64>) 19declare i32 @llvm.ppc.altivec.vextractqm(<1 x i128>) 20 21define i32 @test_vextractbm(<16 x i8> %a) { 22; CHECK-LABEL: test_vextractbm: 23; CHECK: # %bb.0: # %entry 24; CHECK-NEXT: vextractbm r3, v2 25; CHECK-NEXT: blr 26entry: 27 %ext = tail call i32 @llvm.ppc.altivec.vextractbm(<16 x i8> %a) 28 ret i32 %ext 29} 30 31define i32 @test_vextracthm(<8 x i16> %a) { 32; CHECK-LABEL: test_vextracthm: 33; CHECK: # %bb.0: # %entry 34; CHECK-NEXT: vextracthm r3, v2 35; CHECK-NEXT: blr 36entry: 37 %ext = tail call i32 @llvm.ppc.altivec.vextracthm(<8 x i16> %a) 38 ret i32 %ext 39} 40 41define i32 @test_vextractwm(<4 x i32> %a) { 42; CHECK-LABEL: test_vextractwm: 43; CHECK: # %bb.0: # %entry 44; CHECK-NEXT: vextractwm r3, v2 45; CHECK-NEXT: blr 46entry: 47 %ext = tail call i32 @llvm.ppc.altivec.vextractwm(<4 x i32> %a) 48 ret i32 %ext 49} 50 51define i32 @test_vextractdm(<2 x i64> %a) { 52; CHECK-LABEL: test_vextractdm: 53; CHECK: # %bb.0: # %entry 54; CHECK-NEXT: vextractdm r3, v2 55; CHECK-NEXT: blr 56entry: 57 %ext = tail call i32 @llvm.ppc.altivec.vextractdm(<2 x i64> %a) 58 ret i32 %ext 59} 60 61define i32 @test_vextractqm(<1 x i128> %a) { 62; CHECK-LABEL: test_vextractqm: 63; CHECK: # %bb.0: # %entry 64; CHECK-NEXT: vextractqm r3, v2 65; CHECK-NEXT: blr 66entry: 67 %ext = tail call i32 @llvm.ppc.altivec.vextractqm(<1 x i128> %a) 68 ret i32 %ext 69} 70 71declare <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8>) 72declare <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16>) 73declare <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32>) 74declare <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64>) 75declare <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128>) 76 77define <16 x i8> @test_vexpandbm(<16 x i8> %a) { 78; CHECK-LABEL: test_vexpandbm: 79; CHECK: # %bb.0: # %entry 80; CHECK-NEXT: vexpandbm v2, v2 81; CHECK-NEXT: blr 82entry: 83 %exp = tail call <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8> %a) 84 ret <16 x i8> %exp 85} 86 87define <8 x i16> @test_vexpandhm(<8 x i16> %a) { 88; CHECK-LABEL: test_vexpandhm: 89; CHECK: # %bb.0: # %entry 90; CHECK-NEXT: vexpandhm v2, v2 91; CHECK-NEXT: blr 92entry: 93 %exp = tail call <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16> %a) 94 ret <8 x i16> %exp 95} 96 97define <4 x i32> @test_vexpandwm(<4 x i32> %a) { 98; CHECK-LABEL: test_vexpandwm: 99; CHECK: # %bb.0: # %entry 100; CHECK-NEXT: vexpandwm v2, v2 101; CHECK-NEXT: blr 102entry: 103 %exp = tail call <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32> %a) 104 ret <4 x i32> %exp 105} 106 107define <2 x i64> @test_vexpanddm(<2 x i64> %a) { 108; CHECK-LABEL: test_vexpanddm: 109; CHECK: # %bb.0: # %entry 110; CHECK-NEXT: vexpanddm v2, v2 111; CHECK-NEXT: blr 112entry: 113 %exp = tail call <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64> %a) 114 ret <2 x i64> %exp 115} 116 117define <1 x i128> @test_vexpandqm(<1 x i128> %a) { 118; CHECK-LABEL: test_vexpandqm: 119; CHECK: # %bb.0: # %entry 120; CHECK-NEXT: vexpandqm v2, v2 121; CHECK-NEXT: blr 122entry: 123 %exp = tail call <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128> %a) 124 ret <1 x i128> %exp 125} 126 127declare i64 @llvm.ppc.altivec.vcntmbb(<16 x i8>, i32) 128declare i64 @llvm.ppc.altivec.vcntmbh(<8 x i16>, i32) 129declare i64 @llvm.ppc.altivec.vcntmbw(<4 x i32>, i32) 130declare i64 @llvm.ppc.altivec.vcntmbd(<2 x i64>, i32) 131 132define i64 @test_vcntmbb(<16 x i8> %a) { 133; CHECK-LABEL: test_vcntmbb: 134; CHECK: # %bb.0: # %entry 135; CHECK-NEXT: vcntmbb r3, v2, 1 136; CHECK-NEXT: blr 137entry: 138 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbb(<16 x i8> %a, i32 1) 139 ret i64 %cnt 140} 141 142define i64 @test_vcntmbh(<8 x i16> %a) { 143; CHECK-LABEL: test_vcntmbh: 144; CHECK: # %bb.0: # %entry 145; CHECK-NEXT: vcntmbh r3, v2, 0 146; CHECK-NEXT: blr 147entry: 148 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbh(<8 x i16> %a, i32 0) 149 ret i64 %cnt 150} 151 152define i64 @test_vcntmbw(<4 x i32> %a) { 153; CHECK-LABEL: test_vcntmbw: 154; CHECK: # %bb.0: # %entry 155; CHECK-NEXT: vcntmbw r3, v2, 1 156; CHECK-NEXT: blr 157entry: 158 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbw(<4 x i32> %a, i32 1) 159 ret i64 %cnt 160} 161 162define i64 @test_vcntmbd(<2 x i64> %a) { 163; CHECK-LABEL: test_vcntmbd: 164; CHECK: # %bb.0: # %entry 165; CHECK-NEXT: vcntmbd r3, v2, 0 166; CHECK-NEXT: blr 167entry: 168 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbd(<2 x i64> %a, i32 0) 169 ret i64 %cnt 170} 171 172declare <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64) 173declare <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64) 174declare <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64) 175declare <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64) 176declare <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64) 177 178define <16 x i8> @test_mtvsrbm(i64 %a) { 179; CHECK-LABEL: test_mtvsrbm: 180; CHECK: # %bb.0: # %entry 181; CHECK-NEXT: mtvsrbm v2, r3 182; CHECK-NEXT: blr 183entry: 184 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 %a) 185 ret <16 x i8> %mv 186} 187 188define <16 x i8> @test_mtvsrbmi() { 189; CHECK-LABEL: test_mtvsrbmi: 190; CHECK: # %bb.0: # %entry 191; CHECK-NEXT: mtvsrbmi v2, 1 192; CHECK-NEXT: blr 193entry: 194 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 1) 195 ret <16 x i8> %mv 196} 197 198define <16 x i8> @test_mtvsrbmi2() { 199; CHECK-LABEL: test_mtvsrbmi2: 200; CHECK: # %bb.0: # %entry 201; CHECK-NEXT: mtvsrbmi v2, 255 202; CHECK-NEXT: blr 203entry: 204 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 255) 205 ret <16 x i8> %mv 206} 207 208define <16 x i8> @test_mtvsrbmi3() { 209; CHECK-LABEL: test_mtvsrbmi3: 210; CHECK: # %bb.0: # %entry 211; CHECK-NEXT: mtvsrbmi v2, 65535 212; CHECK-NEXT: blr 213entry: 214 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65535) 215 ret <16 x i8> %mv 216} 217 218define <16 x i8> @test_mtvsrbmi4() { 219; CHECK-LABEL: test_mtvsrbmi4: 220; CHECK: # %bb.0: # %entry 221; CHECK-NEXT: mtvsrbmi v2, 0 222; CHECK-NEXT: blr 223entry: 224 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65536) 225 ret <16 x i8> %mv 226} 227 228define <16 x i8> @test_mtvsrbmi5() { 229; CHECK-LABEL: test_mtvsrbmi5: 230; CHECK: # %bb.0: # %entry 231; CHECK-NEXT: mtvsrbmi v2, 10 232; CHECK-NEXT: blr 233entry: 234 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65546) 235 ret <16 x i8> %mv 236} 237 238define <8 x i16> @test_mtvsrhm(i64 %a) { 239; CHECK-LABEL: test_mtvsrhm: 240; CHECK: # %bb.0: # %entry 241; CHECK-NEXT: mtvsrhm v2, r3 242; CHECK-NEXT: blr 243entry: 244 %mv = tail call <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64 %a) 245 ret <8 x i16> %mv 246} 247 248define <4 x i32> @test_mtvsrwm(i64 %a) { 249; CHECK-LABEL: test_mtvsrwm: 250; CHECK: # %bb.0: # %entry 251; CHECK-NEXT: mtvsrwm v2, r3 252; CHECK-NEXT: blr 253entry: 254 %mv = tail call <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64 %a) 255 ret <4 x i32> %mv 256} 257 258define <2 x i64> @test_mtvsrdm(i64 %a) { 259; CHECK-LABEL: test_mtvsrdm: 260; CHECK: # %bb.0: # %entry 261; CHECK-NEXT: mtvsrdm v2, r3 262; CHECK-NEXT: blr 263entry: 264 %mv = tail call <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64 %a) 265 ret <2 x i64> %mv 266} 267 268define <1 x i128> @test_mtvsrqm(i64 %a) { 269; CHECK-LABEL: test_mtvsrqm: 270; CHECK: # %bb.0: # %entry 271; CHECK-NEXT: mtvsrqm v2, r3 272; CHECK-NEXT: blr 273entry: 274 %mv = tail call <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64 %a) 275 ret <1 x i128> %mv 276} 277