1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 3; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s 4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 5; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s 6 7; Function Attrs: norecurse nounwind readnone 8define signext i32 @setbc(float %a, float %b) { 9; CHECK-LABEL: setbc: 10; CHECK: # %bb.0: # %entry 11; CHECK-NEXT: fcmpu cr0, f1, f2 12; CHECK-NEXT: setbc r3, lt 13; CHECK-NEXT: blr 14entry: 15 %cmp = fcmp olt float %a, %b 16 %conv = zext i1 %cmp to i32 17 ret i32 %conv 18} 19 20; Function Attrs: norecurse nounwind readnone 21define signext i32 @setnbc(float %a, float %b) { 22; CHECK-LABEL: setnbc: 23; CHECK: # %bb.0: # %entry 24; CHECK-NEXT: fcmpu cr0, f1, f2 25; CHECK-NEXT: setnbc r3, lt 26; CHECK-NEXT: blr 27entry: 28 %cmp = fcmp olt float %a, %b 29 %sub = sext i1 %cmp to i32 30 ret i32 %sub 31} 32 33; Function Attrs: norecurse nounwind readnone 34define signext i32 @setbcr(float %a, float %b) { 35; CHECK-LABEL: setbcr: 36; CHECK: # %bb.0: # %entry 37; CHECK-NEXT: fcmpu cr0, f1, f2 38; CHECK-NEXT: setbcr r3, lt 39; CHECK-NEXT: blr 40entry: 41 %cmp = fcmp uge float %a, %b 42 %lnot.ext = zext i1 %cmp to i32 43 ret i32 %lnot.ext 44} 45 46; Function Attrs: norecurse nounwind readnone 47define signext i32 @setnbcr(float %a, float %b) { 48; CHECK-LABEL: setnbcr: 49; CHECK: # %bb.0: # %entry 50; CHECK-NEXT: fcmpu cr0, f1, f2 51; CHECK-NEXT: setnbcr r3, lt 52; CHECK-NEXT: blr 53entry: 54 %cmp = fcmp uge float %a, %b 55 %sub = sext i1 %cmp to i32 56 ret i32 %sub 57} 58 59; Function Attrs: norecurse nounwind readnone 60define signext i64 @setbc2(float %a, float %b) { 61; CHECK-LABEL: setbc2: 62; CHECK: # %bb.0: # %entry 63; CHECK-NEXT: fcmpu cr0, f1, f2 64; CHECK-NEXT: setbc r3, lt 65; CHECK-NEXT: blr 66entry: 67 %cmp = fcmp olt float %a, %b 68 %conv = zext i1 %cmp to i64 69 ret i64 %conv 70} 71 72; Function Attrs: norecurse nounwind readnone 73define signext i64 @setnbc2(float %a, float %b) { 74; CHECK-LABEL: setnbc2: 75; CHECK: # %bb.0: # %entry 76; CHECK-NEXT: fcmpu cr0, f1, f2 77; CHECK-NEXT: setnbc r3, lt 78; CHECK-NEXT: blr 79entry: 80 %cmp = fcmp olt float %a, %b 81 %sub = sext i1 %cmp to i64 82 ret i64 %sub 83} 84 85; Function Attrs: norecurse nounwind readnone 86define signext i64 @setbcr2(float %a, float %b) { 87; CHECK-LABEL: setbcr2: 88; CHECK: # %bb.0: # %entry 89; CHECK-NEXT: fcmpu cr0, f1, f2 90; CHECK-NEXT: setbcr r3, lt 91; CHECK-NEXT: blr 92entry: 93 %cmp = fcmp uge float %a, %b 94 %lnot.ext = zext i1 %cmp to i64 95 ret i64 %lnot.ext 96} 97 98; Function Attrs: norecurse nounwind readnone 99define signext i64 @setnbcr2(float %a, float %b) { 100; CHECK-LABEL: setnbcr2: 101; CHECK: # %bb.0: # %entry 102; CHECK-NEXT: fcmpu cr0, f1, f2 103; CHECK-NEXT: setnbcr r3, lt 104; CHECK-NEXT: blr 105entry: 106 %cmp = fcmp uge float %a, %b 107 %sub = sext i1 %cmp to i64 108 ret i64 %sub 109} 110 111; Function Attrs: norecurse nounwind readnone 112define signext i64 @setbc3(double %a, double %b) { 113; CHECK-LABEL: setbc3: 114; CHECK: # %bb.0: # %entry 115; CHECK-NEXT: fcmpu cr0, f1, f2 116; CHECK-NEXT: setbc r3, lt 117; CHECK-NEXT: blr 118entry: 119 %cmp = fcmp olt double %a, %b 120 %conv = zext i1 %cmp to i64 121 ret i64 %conv 122} 123 124; Function Attrs: norecurse nounwind readnone 125define signext i64 @setnbc3(double %a, double %b) { 126; CHECK-LABEL: setnbc3: 127; CHECK: # %bb.0: # %entry 128; CHECK-NEXT: fcmpu cr0, f1, f2 129; CHECK-NEXT: setnbc r3, lt 130; CHECK-NEXT: blr 131entry: 132 %cmp = fcmp olt double %a, %b 133 %sub = sext i1 %cmp to i64 134 ret i64 %sub 135} 136 137; Function Attrs: norecurse nounwind readnone 138define signext i64 @setbcr3(double %a, double %b) { 139; CHECK-LABEL: setbcr3: 140; CHECK: # %bb.0: # %entry 141; CHECK-NEXT: fcmpu cr0, f1, f2 142; CHECK-NEXT: setbcr r3, lt 143; CHECK-NEXT: blr 144entry: 145 %cmp = fcmp uge double %a, %b 146 %lnot.ext = zext i1 %cmp to i64 147 ret i64 %lnot.ext 148} 149 150; Function Attrs: norecurse nounwind readnone 151define signext i64 @setnbcr3(double %a, double %b) { 152; CHECK-LABEL: setnbcr3: 153; CHECK: # %bb.0: # %entry 154; CHECK-NEXT: fcmpu cr0, f1, f2 155; CHECK-NEXT: setnbcr r3, lt 156; CHECK-NEXT: blr 157entry: 158 %cmp = fcmp uge double %a, %b 159 %sub = sext i1 %cmp to i64 160 ret i64 %sub 161} 162 163; Function Attrs: norecurse nounwind readnone 164define signext i32 @setbc4(double %a, double %b) { 165; CHECK-LABEL: setbc4: 166; CHECK: # %bb.0: # %entry 167; CHECK-NEXT: fcmpu cr0, f1, f2 168; CHECK-NEXT: setbc r3, lt 169; CHECK-NEXT: blr 170entry: 171 %cmp = fcmp olt double %a, %b 172 %conv = zext i1 %cmp to i32 173 ret i32 %conv 174} 175 176; Function Attrs: norecurse nounwind readnone 177define signext i32 @setnbc4(double %a, double %b) { 178; CHECK-LABEL: setnbc4: 179; CHECK: # %bb.0: # %entry 180; CHECK-NEXT: fcmpu cr0, f1, f2 181; CHECK-NEXT: setnbc r3, lt 182; CHECK-NEXT: blr 183entry: 184 %cmp = fcmp olt double %a, %b 185 %sub = sext i1 %cmp to i32 186 ret i32 %sub 187} 188 189; Function Attrs: norecurse nounwind readnone 190define signext i32 @setbcr4(double %a, double %b) { 191; CHECK-LABEL: setbcr4: 192; CHECK: # %bb.0: # %entry 193; CHECK-NEXT: fcmpu cr0, f1, f2 194; CHECK-NEXT: setbcr r3, lt 195; CHECK-NEXT: blr 196entry: 197 %cmp = fcmp uge double %a, %b 198 %lnot.ext = zext i1 %cmp to i32 199 ret i32 %lnot.ext 200} 201 202; Function Attrs: norecurse nounwind readnone 203define signext i32 @setnbcr4(double %a, double %b) { 204; CHECK-LABEL: setnbcr4: 205; CHECK: # %bb.0: # %entry 206; CHECK-NEXT: fcmpu cr0, f1, f2 207; CHECK-NEXT: setnbcr r3, lt 208; CHECK-NEXT: blr 209entry: 210 %cmp = fcmp uge double %a, %b 211 %sub = sext i1 %cmp to i32 212 ret i32 %sub 213} 214 215 216; Function Attrs: norecurse nounwind readnone 217define signext i32 @setbc5(float %a, float %b) { 218; CHECK-LABEL: setbc5: 219; CHECK: # %bb.0: # %entry 220; CHECK-NEXT: fcmpu cr0, f1, f2 221; CHECK-NEXT: setbc r3, gt 222; CHECK-NEXT: blr 223entry: 224 %cmp = fcmp ogt float %a, %b 225 %conv = zext i1 %cmp to i32 226 ret i32 %conv 227} 228 229; Function Attrs: norecurse nounwind readnone 230define signext i32 @setnbc5(float %a, float %b) { 231; CHECK-LABEL: setnbc5: 232; CHECK: # %bb.0: # %entry 233; CHECK-NEXT: fcmpu cr0, f1, f2 234; CHECK-NEXT: setnbc r3, gt 235; CHECK-NEXT: blr 236entry: 237 %cmp = fcmp ogt float %a, %b 238 %sub = sext i1 %cmp to i32 239 ret i32 %sub 240} 241 242; Function Attrs: norecurse nounwind readnone 243define signext i32 @setbcr5(float %a, float %b) { 244; CHECK-LABEL: setbcr5: 245; CHECK: # %bb.0: # %entry 246; CHECK-NEXT: fcmpu cr0, f1, f2 247; CHECK-NEXT: setbcr r3, gt 248; CHECK-NEXT: blr 249entry: 250 %cmp = fcmp ule float %a, %b 251 %lnot.ext = zext i1 %cmp to i32 252 ret i32 %lnot.ext 253} 254 255; Function Attrs: norecurse nounwind readnone 256define signext i32 @setnbcr5(float %a, float %b) { 257; CHECK-LABEL: setnbcr5: 258; CHECK: # %bb.0: # %entry 259; CHECK-NEXT: fcmpu cr0, f1, f2 260; CHECK-NEXT: setnbcr r3, gt 261; CHECK-NEXT: blr 262entry: 263 %cmp = fcmp ule float %a, %b 264 %sub = sext i1 %cmp to i32 265 ret i32 %sub 266} 267 268; Function Attrs: norecurse nounwind readnone 269define signext i32 @setbc6(double %a, double %b) { 270; CHECK-LABEL: setbc6: 271; CHECK: # %bb.0: # %entry 272; CHECK-NEXT: fcmpu cr0, f1, f2 273; CHECK-NEXT: setbc r3, gt 274; CHECK-NEXT: blr 275entry: 276 %cmp = fcmp ogt double %a, %b 277 %conv = zext i1 %cmp to i32 278 ret i32 %conv 279} 280 281; Function Attrs: norecurse nounwind readnone 282define signext i32 @setnbc6(double %a, double %b) { 283; CHECK-LABEL: setnbc6: 284; CHECK: # %bb.0: # %entry 285; CHECK-NEXT: fcmpu cr0, f1, f2 286; CHECK-NEXT: setnbc r3, gt 287; CHECK-NEXT: blr 288entry: 289 %cmp = fcmp ogt double %a, %b 290 %sub = sext i1 %cmp to i32 291 ret i32 %sub 292} 293 294; Function Attrs: norecurse nounwind readnone 295define signext i32 @setbcr6(double %a, double %b) { 296; CHECK-LABEL: setbcr6: 297; CHECK: # %bb.0: # %entry 298; CHECK-NEXT: fcmpu cr0, f1, f2 299; CHECK-NEXT: setbcr r3, gt 300; CHECK-NEXT: blr 301entry: 302 %cmp = fcmp ule double %a, %b 303 %lnot.ext = zext i1 %cmp to i32 304 ret i32 %lnot.ext 305} 306 307; Function Attrs: norecurse nounwind readnone 308define signext i32 @setnbcr6(double %a, double %b) { 309; CHECK-LABEL: setnbcr6: 310; CHECK: # %bb.0: # %entry 311; CHECK-NEXT: fcmpu cr0, f1, f2 312; CHECK-NEXT: setnbcr r3, gt 313; CHECK-NEXT: blr 314entry: 315 %cmp = fcmp ule double %a, %b 316 %sub = sext i1 %cmp to i32 317 ret i32 %sub 318} 319 320; Function Attrs: norecurse nounwind readnone 321define signext i64 @setbc7(float %a, float %b) { 322; CHECK-LABEL: setbc7: 323; CHECK: # %bb.0: # %entry 324; CHECK-NEXT: fcmpu cr0, f1, f2 325; CHECK-NEXT: setbc r3, gt 326; CHECK-NEXT: blr 327entry: 328 %cmp = fcmp ogt float %a, %b 329 %conv = zext i1 %cmp to i64 330 ret i64 %conv 331} 332 333; Function Attrs: norecurse nounwind readnone 334define signext i64 @setnbc7(float %a, float %b) { 335; CHECK-LABEL: setnbc7: 336; CHECK: # %bb.0: # %entry 337; CHECK-NEXT: fcmpu cr0, f1, f2 338; CHECK-NEXT: setnbc r3, gt 339; CHECK-NEXT: blr 340entry: 341 %cmp = fcmp ogt float %a, %b 342 %sub = sext i1 %cmp to i64 343 ret i64 %sub 344} 345 346; Function Attrs: norecurse nounwind readnone 347define signext i64 @setbcr7(float %a, float %b) { 348; CHECK-LABEL: setbcr7: 349; CHECK: # %bb.0: # %entry 350; CHECK-NEXT: fcmpu cr0, f1, f2 351; CHECK-NEXT: setbcr r3, gt 352; CHECK-NEXT: blr 353entry: 354 %cmp = fcmp ule float %a, %b 355 %lnot.ext = zext i1 %cmp to i64 356 ret i64 %lnot.ext 357} 358 359; Function Attrs: norecurse nounwind readnone 360define signext i64 @setnbcr7(float %a, float %b) { 361; CHECK-LABEL: setnbcr7: 362; CHECK: # %bb.0: # %entry 363; CHECK-NEXT: fcmpu cr0, f1, f2 364; CHECK-NEXT: setnbcr r3, gt 365; CHECK-NEXT: blr 366entry: 367 %cmp = fcmp ule float %a, %b 368 %sub = sext i1 %cmp to i64 369 ret i64 %sub 370} 371 372; Function Attrs: norecurse nounwind readnone 373define signext i64 @setbc8(double %a, double %b) { 374; CHECK-LABEL: setbc8: 375; CHECK: # %bb.0: # %entry 376; CHECK-NEXT: fcmpu cr0, f1, f2 377; CHECK-NEXT: setbc r3, gt 378; CHECK-NEXT: blr 379entry: 380 %cmp = fcmp ogt double %a, %b 381 %conv = zext i1 %cmp to i64 382 ret i64 %conv 383} 384 385; Function Attrs: norecurse nounwind readnone 386define signext i64 @setnbc8(double %a, double %b) { 387; CHECK-LABEL: setnbc8: 388; CHECK: # %bb.0: # %entry 389; CHECK-NEXT: fcmpu cr0, f1, f2 390; CHECK-NEXT: setnbc r3, gt 391; CHECK-NEXT: blr 392entry: 393 %cmp = fcmp ogt double %a, %b 394 %sub = sext i1 %cmp to i64 395 ret i64 %sub 396} 397 398; Function Attrs: norecurse nounwind readnone 399define signext i64 @setbcr8(double %a, double %b) { 400; CHECK-LABEL: setbcr8: 401; CHECK: # %bb.0: # %entry 402; CHECK-NEXT: fcmpu cr0, f1, f2 403; CHECK-NEXT: setbcr r3, gt 404; CHECK-NEXT: blr 405entry: 406 %cmp = fcmp ule double %a, %b 407 %lnot.ext = zext i1 %cmp to i64 408 ret i64 %lnot.ext 409} 410 411; Function Attrs: norecurse nounwind readnone 412define signext i64 @setnbcr8(double %a, double %b) { 413; CHECK-LABEL: setnbcr8: 414; CHECK: # %bb.0: # %entry 415; CHECK-NEXT: fcmpu cr0, f1, f2 416; CHECK-NEXT: setnbcr r3, gt 417; CHECK-NEXT: blr 418entry: 419 %cmp = fcmp ule double %a, %b 420 %sub = sext i1 %cmp to i64 421 ret i64 %sub 422} 423 424; Function Attrs: norecurse nounwind readnone 425define signext i32 @setbc9(float %a, float %b) { 426; CHECK-LABEL: setbc9: 427; CHECK: # %bb.0: # %entry 428; CHECK-NEXT: fcmpu cr0, f1, f2 429; CHECK-NEXT: setbc r3, eq 430; CHECK-NEXT: blr 431entry: 432 %cmp = fcmp oeq float %a, %b 433 %conv = zext i1 %cmp to i32 434 ret i32 %conv 435} 436 437; Function Attrs: norecurse nounwind readnone 438define signext i32 @setnbc9(float %a, float %b) { 439; CHECK-LABEL: setnbc9: 440; CHECK: # %bb.0: # %entry 441; CHECK-NEXT: fcmpu cr0, f1, f2 442; CHECK-NEXT: setnbc r3, eq 443; CHECK-NEXT: blr 444entry: 445 %cmp = fcmp oeq float %a, %b 446 %sub = sext i1 %cmp to i32 447 ret i32 %sub 448} 449 450; Function Attrs: norecurse nounwind readnone 451define signext i32 @setbcr9(float %a, float %b) { 452; CHECK-LABEL: setbcr9: 453; CHECK: # %bb.0: # %entry 454; CHECK-NEXT: fcmpu cr0, f1, f2 455; CHECK-NEXT: setbcr r3, eq 456; CHECK-NEXT: blr 457entry: 458 %cmp = fcmp une float %a, %b 459 %lnot.ext = zext i1 %cmp to i32 460 ret i32 %lnot.ext 461} 462 463; Function Attrs: norecurse nounwind readnone 464define signext i32 @setnbcr9(float %a, float %b) { 465; CHECK-LABEL: setnbcr9: 466; CHECK: # %bb.0: # %entry 467; CHECK-NEXT: fcmpu cr0, f1, f2 468; CHECK-NEXT: setnbcr r3, eq 469; CHECK-NEXT: blr 470entry: 471 %cmp = fcmp une float %a, %b 472 %sub = sext i1 %cmp to i32 473 ret i32 %sub 474} 475 476; Function Attrs: norecurse nounwind readnone 477define signext i32 @setbc10(double %a, double %b) { 478; CHECK-LABEL: setbc10: 479; CHECK: # %bb.0: # %entry 480; CHECK-NEXT: fcmpu cr0, f1, f2 481; CHECK-NEXT: setbc r3, eq 482; CHECK-NEXT: blr 483entry: 484 %cmp = fcmp oeq double %a, %b 485 %conv = zext i1 %cmp to i32 486 ret i32 %conv 487} 488 489; Function Attrs: norecurse nounwind readnone 490define signext i32 @setnbc10(double %a, double %b) { 491; CHECK-LABEL: setnbc10: 492; CHECK: # %bb.0: # %entry 493; CHECK-NEXT: fcmpu cr0, f1, f2 494; CHECK-NEXT: setnbc r3, eq 495; CHECK-NEXT: blr 496entry: 497 %cmp = fcmp oeq double %a, %b 498 %sub = sext i1 %cmp to i32 499 ret i32 %sub 500} 501 502; Function Attrs: norecurse nounwind readnone 503define signext i32 @setbcr10(double %a, double %b) { 504; CHECK-LABEL: setbcr10: 505; CHECK: # %bb.0: # %entry 506; CHECK-NEXT: fcmpu cr0, f1, f2 507; CHECK-NEXT: setbcr r3, eq 508; CHECK-NEXT: blr 509entry: 510 %cmp = fcmp une double %a, %b 511 %lnot.ext = zext i1 %cmp to i32 512 ret i32 %lnot.ext 513} 514 515; Function Attrs: norecurse nounwind readnone 516define signext i32 @setnbcr10(double %a, double %b) { 517; CHECK-LABEL: setnbcr10: 518; CHECK: # %bb.0: # %entry 519; CHECK-NEXT: fcmpu cr0, f1, f2 520; CHECK-NEXT: setnbcr r3, eq 521; CHECK-NEXT: blr 522entry: 523 %cmp = fcmp une double %a, %b 524 %sub = sext i1 %cmp to i32 525 ret i32 %sub 526} 527 528; Function Attrs: norecurse nounwind readnone 529define signext i64 @setbc11(float %a, float %b) { 530; CHECK-LABEL: setbc11: 531; CHECK: # %bb.0: # %entry 532; CHECK-NEXT: fcmpu cr0, f1, f2 533; CHECK-NEXT: setbc r3, eq 534; CHECK-NEXT: blr 535entry: 536 %cmp = fcmp oeq float %a, %b 537 %conv = zext i1 %cmp to i64 538 ret i64 %conv 539} 540 541; Function Attrs: norecurse nounwind readnone 542define signext i64 @setnbc11(float %a, float %b) { 543; CHECK-LABEL: setnbc11: 544; CHECK: # %bb.0: # %entry 545; CHECK-NEXT: fcmpu cr0, f1, f2 546; CHECK-NEXT: setnbc r3, eq 547; CHECK-NEXT: blr 548entry: 549 %cmp = fcmp oeq float %a, %b 550 %sub = sext i1 %cmp to i64 551 ret i64 %sub 552} 553 554; Function Attrs: norecurse nounwind readnone 555define signext i64 @setbcr11(float %a, float %b) { 556; CHECK-LABEL: setbcr11: 557; CHECK: # %bb.0: # %entry 558; CHECK-NEXT: fcmpu cr0, f1, f2 559; CHECK-NEXT: setbcr r3, eq 560; CHECK-NEXT: blr 561entry: 562 %cmp = fcmp une float %a, %b 563 %lnot.ext = zext i1 %cmp to i64 564 ret i64 %lnot.ext 565} 566 567; Function Attrs: norecurse nounwind readnone 568define signext i64 @setnbcr11(float %a, float %b) { 569; CHECK-LABEL: setnbcr11: 570; CHECK: # %bb.0: # %entry 571; CHECK-NEXT: fcmpu cr0, f1, f2 572; CHECK-NEXT: setnbcr r3, eq 573; CHECK-NEXT: blr 574entry: 575 %cmp = fcmp une float %a, %b 576 %sub = sext i1 %cmp to i64 577 ret i64 %sub 578} 579 580; Function Attrs: norecurse nounwind readnone 581define signext i64 @setbc12(double %a, double %b) { 582; CHECK-LABEL: setbc12: 583; CHECK: # %bb.0: # %entry 584; CHECK-NEXT: fcmpu cr0, f1, f2 585; CHECK-NEXT: setbc r3, eq 586; CHECK-NEXT: blr 587entry: 588 %cmp = fcmp oeq double %a, %b 589 %conv = zext i1 %cmp to i64 590 ret i64 %conv 591} 592 593; Function Attrs: norecurse nounwind readnone 594define signext i64 @setnbc12(double %a, double %b) { 595; CHECK-LABEL: setnbc12: 596; CHECK: # %bb.0: # %entry 597; CHECK-NEXT: fcmpu cr0, f1, f2 598; CHECK-NEXT: setnbc r3, eq 599; CHECK-NEXT: blr 600entry: 601 %cmp = fcmp oeq double %a, %b 602 %sub = sext i1 %cmp to i64 603 ret i64 %sub 604} 605 606; Function Attrs: norecurse nounwind readnone 607define signext i64 @setbcr12(double %a, double %b) { 608; CHECK-LABEL: setbcr12: 609; CHECK: # %bb.0: # %entry 610; CHECK-NEXT: fcmpu cr0, f1, f2 611; CHECK-NEXT: setbcr r3, eq 612; CHECK-NEXT: blr 613entry: 614 %cmp = fcmp une double %a, %b 615 %lnot.ext = zext i1 %cmp to i64 616 ret i64 %lnot.ext 617} 618 619; Function Attrs: norecurse nounwind readnone 620define signext i64 @setnbcr12(double %a, double %b) { 621; CHECK-LABEL: setnbcr12: 622; CHECK: # %bb.0: # %entry 623; CHECK-NEXT: fcmpu cr0, f1, f2 624; CHECK-NEXT: setnbcr r3, eq 625; CHECK-NEXT: blr 626entry: 627 %cmp = fcmp une double %a, %b 628 %sub = sext i1 %cmp to i64 629 ret i64 %sub 630} 631 632; Function Attrs: norecurse nounwind readnone 633define signext i32 @setbc13(float %a, float %b) { 634; CHECK-LABEL: setbc13: 635; CHECK: # %bb.0: # %entry 636; CHECK-NEXT: fcmpu cr0, f1, f2 637; CHECK-NEXT: setbc r3, un 638; CHECK-NEXT: blr 639entry: 640 %cmp = fcmp uno float %a, %b 641 %conv = zext i1 %cmp to i32 642 ret i32 %conv 643} 644 645; Function Attrs: norecurse nounwind readnone 646define signext i32 @setnbc13(float %a, float %b) { 647; CHECK-LABEL: setnbc13: 648; CHECK: # %bb.0: # %entry 649; CHECK-NEXT: fcmpu cr0, f1, f2 650; CHECK-NEXT: setnbc r3, un 651; CHECK-NEXT: blr 652entry: 653 %cmp = fcmp uno float %a, %b 654 %sub = sext i1 %cmp to i32 655 ret i32 %sub 656} 657 658; Function Attrs: norecurse nounwind readnone 659define signext i32 @setbcr13(float %a, float %b) { 660; CHECK-LABEL: setbcr13: 661; CHECK: # %bb.0: # %entry 662; CHECK-NEXT: fcmpu cr0, f1, f2 663; CHECK-NEXT: setbcr r3, un 664; CHECK-NEXT: blr 665entry: 666 %cmp = fcmp ord float %a, %b 667 %lnot.ext = zext i1 %cmp to i32 668 ret i32 %lnot.ext 669} 670 671; Function Attrs: norecurse nounwind readnone 672define signext i32 @setnbcr13(float %a, float %b) { 673; CHECK-LABEL: setnbcr13: 674; CHECK: # %bb.0: # %entry 675; CHECK-NEXT: fcmpu cr0, f1, f2 676; CHECK-NEXT: setnbcr r3, un 677; CHECK-NEXT: blr 678entry: 679 %cmp = fcmp ord float %a, %b 680 %sub = sext i1 %cmp to i32 681 ret i32 %sub 682} 683 684; Function Attrs: norecurse nounwind readnone 685define signext i32 @setbc14(double %a, double %b) { 686; CHECK-LABEL: setbc14: 687; CHECK: # %bb.0: # %entry 688; CHECK-NEXT: fcmpu cr0, f1, f2 689; CHECK-NEXT: setbc r3, un 690; CHECK-NEXT: blr 691entry: 692 %cmp = fcmp uno double %a, %b 693 %conv = zext i1 %cmp to i32 694 ret i32 %conv 695} 696 697; Function Attrs: norecurse nounwind readnone 698define signext i32 @setnbc14(double %a, double %b) { 699; CHECK-LABEL: setnbc14: 700; CHECK: # %bb.0: # %entry 701; CHECK-NEXT: fcmpu cr0, f1, f2 702; CHECK-NEXT: setnbc r3, un 703; CHECK-NEXT: blr 704entry: 705 %cmp = fcmp uno double %a, %b 706 %sub = sext i1 %cmp to i32 707 ret i32 %sub 708} 709 710; Function Attrs: norecurse nounwind readnone 711define signext i32 @setbcr14(double %a, double %b) { 712; CHECK-LABEL: setbcr14: 713; CHECK: # %bb.0: # %entry 714; CHECK-NEXT: fcmpu cr0, f1, f2 715; CHECK-NEXT: setbcr r3, un 716; CHECK-NEXT: blr 717entry: 718 %cmp = fcmp ord double %a, %b 719 %lnot.ext = zext i1 %cmp to i32 720 ret i32 %lnot.ext 721} 722 723; Function Attrs: norecurse nounwind readnone 724define signext i32 @setnbcr14(double %a, double %b) { 725; CHECK-LABEL: setnbcr14: 726; CHECK: # %bb.0: # %entry 727; CHECK-NEXT: fcmpu cr0, f1, f2 728; CHECK-NEXT: setnbcr r3, un 729; CHECK-NEXT: blr 730entry: 731 %cmp = fcmp ord double %a, %b 732 %sub = sext i1 %cmp to i32 733 ret i32 %sub 734} 735 736; Function Attrs: norecurse nounwind readnone 737define signext i64 @setbc15(float %a, float %b) { 738; CHECK-LABEL: setbc15: 739; CHECK: # %bb.0: # %entry 740; CHECK-NEXT: fcmpu cr0, f1, f2 741; CHECK-NEXT: setbc r3, un 742; CHECK-NEXT: blr 743entry: 744 %cmp = fcmp uno float %a, %b 745 %conv = zext i1 %cmp to i64 746 ret i64 %conv 747} 748 749; Function Attrs: norecurse nounwind readnone 750define signext i64 @setnbc15(float %a, float %b) { 751; CHECK-LABEL: setnbc15: 752; CHECK: # %bb.0: # %entry 753; CHECK-NEXT: fcmpu cr0, f1, f2 754; CHECK-NEXT: setnbc r3, un 755; CHECK-NEXT: blr 756entry: 757 %cmp = fcmp uno float %a, %b 758 %sub = sext i1 %cmp to i64 759 ret i64 %sub 760} 761 762; Function Attrs: norecurse nounwind readnone 763define signext i64 @setbcr15(float %a, float %b) { 764; CHECK-LABEL: setbcr15: 765; CHECK: # %bb.0: # %entry 766; CHECK-NEXT: fcmpu cr0, f1, f2 767; CHECK-NEXT: setbcr r3, un 768; CHECK-NEXT: blr 769entry: 770 %cmp = fcmp ord float %a, %b 771 %lnot.ext = zext i1 %cmp to i64 772 ret i64 %lnot.ext 773} 774 775; Function Attrs: norecurse nounwind readnone 776define signext i64 @setnbcr15(float %a, float %b) { 777; CHECK-LABEL: setnbcr15: 778; CHECK: # %bb.0: # %entry 779; CHECK-NEXT: fcmpu cr0, f1, f2 780; CHECK-NEXT: setnbcr r3, un 781; CHECK-NEXT: blr 782entry: 783 %cmp = fcmp ord float %a, %b 784 %sub = sext i1 %cmp to i64 785 ret i64 %sub 786} 787 788; Function Attrs: norecurse nounwind readnone 789define signext i64 @setbc16(double %a, double %b) { 790; CHECK-LABEL: setbc16: 791; CHECK: # %bb.0: # %entry 792; CHECK-NEXT: fcmpu cr0, f1, f2 793; CHECK-NEXT: setbc r3, un 794; CHECK-NEXT: blr 795entry: 796 %cmp = fcmp uno double %a, %b 797 %conv = zext i1 %cmp to i64 798 ret i64 %conv 799} 800 801; Function Attrs: norecurse nounwind readnone 802define signext i64 @setnbc16(double %a, double %b) { 803; CHECK-LABEL: setnbc16: 804; CHECK: # %bb.0: # %entry 805; CHECK-NEXT: fcmpu cr0, f1, f2 806; CHECK-NEXT: setnbc r3, un 807; CHECK-NEXT: blr 808entry: 809 %cmp = fcmp uno double %a, %b 810 %sub = sext i1 %cmp to i64 811 ret i64 %sub 812} 813 814; Function Attrs: norecurse nounwind readnone 815define signext i64 @setbcr16(double %a, double %b) { 816; CHECK-LABEL: setbcr16: 817; CHECK: # %bb.0: # %entry 818; CHECK-NEXT: fcmpu cr0, f1, f2 819; CHECK-NEXT: setbcr r3, un 820; CHECK-NEXT: blr 821entry: 822 %cmp = fcmp ord double %a, %b 823 %lnot.ext = zext i1 %cmp to i64 824 ret i64 %lnot.ext 825} 826 827; Function Attrs: norecurse nounwind readnone 828define signext i64 @setnbcr16(double %a, double %b) { 829; CHECK-LABEL: setnbcr16: 830; CHECK: # %bb.0: # %entry 831; CHECK-NEXT: fcmpu cr0, f1, f2 832; CHECK-NEXT: setnbcr r3, un 833; CHECK-NEXT: blr 834entry: 835 %cmp = fcmp ord double %a, %b 836 %sub = sext i1 %cmp to i64 837 ret i64 %sub 838} 839 840define signext i32 @setbc17(float %a, float %b) { 841; CHECK-LABEL: setbc17: 842; CHECK: # %bb.0: # %entry 843; CHECK-NEXT: fcmpu cr0, f1, f2 844; CHECK-NEXT: cror 4*cr5+lt, lt, un 845; CHECK-NEXT: setbc r3, 4*cr5+lt 846; CHECK-NEXT: blr 847entry: 848 %cmp = fcmp ult float %a, %b 849 %conv = zext i1 %cmp to i32 850 ret i32 %conv 851} 852 853define signext i32 @setnbc17(float %a, float %b) { 854; CHECK-LABEL: setnbc17: 855; CHECK: # %bb.0: # %entry 856; CHECK-NEXT: fcmpu cr0, f1, f2 857; CHECK-NEXT: cror 4*cr5+lt, lt, un 858; CHECK-NEXT: setnbc r3, 4*cr5+lt 859; CHECK-NEXT: blr 860entry: 861 %cmp = fcmp ult float %a, %b 862 %conv = sext i1 %cmp to i32 863 ret i32 %conv 864} 865 866define signext i32 @setbc18(double %a, double %b) { 867; CHECK-LABEL: setbc18: 868; CHECK: # %bb.0: # %entry 869; CHECK-NEXT: fcmpu cr0, f1, f2 870; CHECK-NEXT: cror 4*cr5+lt, lt, un 871; CHECK-NEXT: setbc r3, 4*cr5+lt 872; CHECK-NEXT: blr 873entry: 874 %cmp = fcmp ult double %a, %b 875 %conv = zext i1 %cmp to i32 876 ret i32 %conv 877} 878 879define signext i32 @setnbc18(double %a, double %b) { 880; CHECK-LABEL: setnbc18: 881; CHECK: # %bb.0: # %entry 882; CHECK-NEXT: fcmpu cr0, f1, f2 883; CHECK-NEXT: cror 4*cr5+lt, lt, un 884; CHECK-NEXT: setnbc r3, 4*cr5+lt 885; CHECK-NEXT: blr 886entry: 887 %cmp = fcmp ult double %a, %b 888 %conv = sext i1 %cmp to i32 889 ret i32 %conv 890} 891 892define signext i64 @setbc19(float %a, float %b) { 893; CHECK-LABEL: setbc19: 894; CHECK: # %bb.0: # %entry 895; CHECK-NEXT: fcmpu cr0, f1, f2 896; CHECK-NEXT: cror 4*cr5+lt, lt, un 897; CHECK-NEXT: setbc r3, 4*cr5+lt 898; CHECK-NEXT: blr 899entry: 900 %cmp = fcmp ult float %a, %b 901 %conv = zext i1 %cmp to i64 902 ret i64 %conv 903} 904 905define signext i64 @setnbc19(float %a, float %b) { 906; CHECK-LABEL: setnbc19: 907; CHECK: # %bb.0: # %entry 908; CHECK-NEXT: fcmpu cr0, f1, f2 909; CHECK-NEXT: cror 4*cr5+lt, lt, un 910; CHECK-NEXT: setnbc r3, 4*cr5+lt 911; CHECK-NEXT: blr 912entry: 913 %cmp = fcmp ult float %a, %b 914 %conv = sext i1 %cmp to i64 915 ret i64 %conv 916} 917 918define signext i64 @setbc20(double %a, double %b) { 919; CHECK-LABEL: setbc20: 920; CHECK: # %bb.0: # %entry 921; CHECK-NEXT: fcmpu cr0, f1, f2 922; CHECK-NEXT: cror 4*cr5+lt, lt, un 923; CHECK-NEXT: setbc r3, 4*cr5+lt 924; CHECK-NEXT: blr 925entry: 926 %cmp = fcmp ult double %a, %b 927 %conv = zext i1 %cmp to i64 928 ret i64 %conv 929} 930 931define signext i64 @setnbc20(double %a, double %b) { 932; CHECK-LABEL: setnbc20: 933; CHECK: # %bb.0: # %entry 934; CHECK-NEXT: fcmpu cr0, f1, f2 935; CHECK-NEXT: cror 4*cr5+lt, lt, un 936; CHECK-NEXT: setnbc r3, 4*cr5+lt 937; CHECK-NEXT: blr 938entry: 939 %cmp = fcmp ult double %a, %b 940 %conv = sext i1 %cmp to i64 941 ret i64 %conv 942} 943 944define signext i32 @setbc21(float %a, float %b) { 945; CHECK-LABEL: setbc21: 946; CHECK: # %bb.0: # %entry 947; CHECK-NEXT: fcmpu cr0, f1, f2 948; CHECK-NEXT: crnor 4*cr5+lt, un, lt 949; CHECK-NEXT: setbc r3, 4*cr5+lt 950; CHECK-NEXT: blr 951entry: 952 %cmp = fcmp oge float %a, %b 953 %conv = zext i1 %cmp to i32 954 ret i32 %conv 955} 956 957define signext i32 @setnbc21(float %a, float %b) { 958; CHECK-LABEL: setnbc21: 959; CHECK: # %bb.0: # %entry 960; CHECK-NEXT: fcmpu cr0, f1, f2 961; CHECK-NEXT: crnor 4*cr5+lt, un, lt 962; CHECK-NEXT: setnbc r3, 4*cr5+lt 963; CHECK-NEXT: blr 964entry: 965 %cmp = fcmp oge float %a, %b 966 %conv = sext i1 %cmp to i32 967 ret i32 %conv 968} 969 970define signext i32 @setbc22(double %a, double %b) { 971; CHECK-LABEL: setbc22: 972; CHECK: # %bb.0: # %entry 973; CHECK-NEXT: fcmpu cr0, f1, f2 974; CHECK-NEXT: crnor 4*cr5+lt, un, lt 975; CHECK-NEXT: setbc r3, 4*cr5+lt 976; CHECK-NEXT: blr 977entry: 978 %cmp = fcmp oge double %a, %b 979 %conv = zext i1 %cmp to i32 980 ret i32 %conv 981} 982 983define signext i32 @setnbc22(double %a, double %b) { 984; CHECK-LABEL: setnbc22: 985; CHECK: # %bb.0: # %entry 986; CHECK-NEXT: fcmpu cr0, f1, f2 987; CHECK-NEXT: crnor 4*cr5+lt, un, lt 988; CHECK-NEXT: setnbc r3, 4*cr5+lt 989; CHECK-NEXT: blr 990entry: 991 %cmp = fcmp oge double %a, %b 992 %conv = sext i1 %cmp to i32 993 ret i32 %conv 994} 995 996define signext i64 @setbc23(float %a, float %b) { 997; CHECK-LABEL: setbc23: 998; CHECK: # %bb.0: # %entry 999; CHECK-NEXT: fcmpu cr0, f1, f2 1000; CHECK-NEXT: crnor 4*cr5+lt, un, lt 1001; CHECK-NEXT: setbc r3, 4*cr5+lt 1002; CHECK-NEXT: blr 1003entry: 1004 %cmp = fcmp oge float %a, %b 1005 %conv = zext i1 %cmp to i64 1006 ret i64 %conv 1007} 1008 1009define signext i64 @setnbc23(float %a, float %b) { 1010; CHECK-LABEL: setnbc23: 1011; CHECK: # %bb.0: # %entry 1012; CHECK-NEXT: fcmpu cr0, f1, f2 1013; CHECK-NEXT: crnor 4*cr5+lt, un, lt 1014; CHECK-NEXT: setnbc r3, 4*cr5+lt 1015; CHECK-NEXT: blr 1016entry: 1017 %cmp = fcmp oge float %a, %b 1018 %conv = sext i1 %cmp to i64 1019 ret i64 %conv 1020} 1021 1022define signext i64 @setbc24(double %a, double %b) { 1023; CHECK-LABEL: setbc24: 1024; CHECK: # %bb.0: # %entry 1025; CHECK-NEXT: fcmpu cr0, f1, f2 1026; CHECK-NEXT: crnor 4*cr5+lt, un, lt 1027; CHECK-NEXT: setbc r3, 4*cr5+lt 1028; CHECK-NEXT: blr 1029entry: 1030 %cmp = fcmp oge double %a, %b 1031 %conv = zext i1 %cmp to i64 1032 ret i64 %conv 1033} 1034 1035define signext i64 @setnbc24(double %a, double %b) { 1036; CHECK-LABEL: setnbc24: 1037; CHECK: # %bb.0: # %entry 1038; CHECK-NEXT: fcmpu cr0, f1, f2 1039; CHECK-NEXT: crnor 4*cr5+lt, un, lt 1040; CHECK-NEXT: setnbc r3, 4*cr5+lt 1041; CHECK-NEXT: blr 1042entry: 1043 %cmp = fcmp oge double %a, %b 1044 %conv = sext i1 %cmp to i64 1045 ret i64 %conv 1046} 1047 1048define signext i32 @setbc25(float %a, float %b) { 1049; CHECK-LABEL: setbc25: 1050; CHECK: # %bb.0: # %entry 1051; CHECK-NEXT: fcmpu cr0, f1, f2 1052; CHECK-NEXT: crnor 4*cr5+lt, un, gt 1053; CHECK-NEXT: setbc r3, 4*cr5+lt 1054; CHECK-NEXT: blr 1055entry: 1056 %cmp = fcmp ole float %a, %b 1057 %conv = zext i1 %cmp to i32 1058 ret i32 %conv 1059} 1060 1061define signext i32 @setnbc25(float %a, float %b) { 1062; CHECK-LABEL: setnbc25: 1063; CHECK: # %bb.0: # %entry 1064; CHECK-NEXT: fcmpu cr0, f1, f2 1065; CHECK-NEXT: crnor 4*cr5+lt, un, gt 1066; CHECK-NEXT: setnbc r3, 4*cr5+lt 1067; CHECK-NEXT: blr 1068entry: 1069 %cmp = fcmp ole float %a, %b 1070 %conv = sext i1 %cmp to i32 1071 ret i32 %conv 1072} 1073 1074define signext i32 @setbc26(double %a, double %b) { 1075; CHECK-LABEL: setbc26: 1076; CHECK: # %bb.0: # %entry 1077; CHECK-NEXT: fcmpu cr0, f1, f2 1078; CHECK-NEXT: crnor 4*cr5+lt, un, gt 1079; CHECK-NEXT: setbc r3, 4*cr5+lt 1080; CHECK-NEXT: blr 1081entry: 1082 %cmp = fcmp ole double %a, %b 1083 %conv = zext i1 %cmp to i32 1084 ret i32 %conv 1085} 1086 1087define signext i32 @setnbc26(double %a, double %b) { 1088; CHECK-LABEL: setnbc26: 1089; CHECK: # %bb.0: # %entry 1090; CHECK-NEXT: fcmpu cr0, f1, f2 1091; CHECK-NEXT: crnor 4*cr5+lt, un, gt 1092; CHECK-NEXT: setnbc r3, 4*cr5+lt 1093; CHECK-NEXT: blr 1094entry: 1095 %cmp = fcmp ole double %a, %b 1096 %conv = sext i1 %cmp to i32 1097 ret i32 %conv 1098} 1099 1100define signext i64 @setbc27(float %a, float %b) { 1101; CHECK-LABEL: setbc27: 1102; CHECK: # %bb.0: # %entry 1103; CHECK-NEXT: fcmpu cr0, f1, f2 1104; CHECK-NEXT: crnor 4*cr5+lt, un, gt 1105; CHECK-NEXT: setbc r3, 4*cr5+lt 1106; CHECK-NEXT: blr 1107entry: 1108 %cmp = fcmp ole float %a, %b 1109 %conv = zext i1 %cmp to i64 1110 ret i64 %conv 1111} 1112 1113define signext i64 @setnbc27(float %a, float %b) { 1114; CHECK-LABEL: setnbc27: 1115; CHECK: # %bb.0: # %entry 1116; CHECK-NEXT: fcmpu cr0, f1, f2 1117; CHECK-NEXT: crnor 4*cr5+lt, un, gt 1118; CHECK-NEXT: setnbc r3, 4*cr5+lt 1119; CHECK-NEXT: blr 1120entry: 1121 %cmp = fcmp ole float %a, %b 1122 %conv = sext i1 %cmp to i64 1123 ret i64 %conv 1124} 1125 1126define signext i64 @setbc28(double %a, double %b) { 1127; CHECK-LABEL: setbc28: 1128; CHECK: # %bb.0: # %entry 1129; CHECK-NEXT: fcmpu cr0, f1, f2 1130; CHECK-NEXT: crnor 4*cr5+lt, un, gt 1131; CHECK-NEXT: setbc r3, 4*cr5+lt 1132; CHECK-NEXT: blr 1133entry: 1134 %cmp = fcmp ole double %a, %b 1135 %conv = zext i1 %cmp to i64 1136 ret i64 %conv 1137} 1138 1139define signext i64 @setnbc28(double %a, double %b) { 1140; CHECK-LABEL: setnbc28: 1141; CHECK: # %bb.0: # %entry 1142; CHECK-NEXT: fcmpu cr0, f1, f2 1143; CHECK-NEXT: crnor 4*cr5+lt, un, gt 1144; CHECK-NEXT: setnbc r3, 4*cr5+lt 1145; CHECK-NEXT: blr 1146entry: 1147 %cmp = fcmp ole double %a, %b 1148 %conv = sext i1 %cmp to i64 1149 ret i64 %conv 1150} 1151 1152define signext i32 @setbc29(float %a, float %b) { 1153; CHECK-LABEL: setbc29: 1154; CHECK: # %bb.0: # %entry 1155; CHECK-NEXT: fcmpu cr0, f1, f2 1156; CHECK-NEXT: cror 4*cr5+lt, gt, un 1157; CHECK-NEXT: setbc r3, 4*cr5+lt 1158; CHECK-NEXT: blr 1159entry: 1160 %cmp = fcmp ugt float %a, %b 1161 %conv = zext i1 %cmp to i32 1162 ret i32 %conv 1163} 1164 1165define signext i32 @setnbc29(float %a, float %b) { 1166; CHECK-LABEL: setnbc29: 1167; CHECK: # %bb.0: # %entry 1168; CHECK-NEXT: fcmpu cr0, f1, f2 1169; CHECK-NEXT: cror 4*cr5+lt, gt, un 1170; CHECK-NEXT: setnbc r3, 4*cr5+lt 1171; CHECK-NEXT: blr 1172entry: 1173 %cmp = fcmp ugt float %a, %b 1174 %conv = sext i1 %cmp to i32 1175 ret i32 %conv 1176} 1177 1178define signext i32 @setbc30(double %a, double %b) { 1179; CHECK-LABEL: setbc30: 1180; CHECK: # %bb.0: # %entry 1181; CHECK-NEXT: fcmpu cr0, f1, f2 1182; CHECK-NEXT: cror 4*cr5+lt, gt, un 1183; CHECK-NEXT: setbc r3, 4*cr5+lt 1184; CHECK-NEXT: blr 1185entry: 1186 %cmp = fcmp ugt double %a, %b 1187 %conv = zext i1 %cmp to i32 1188 ret i32 %conv 1189} 1190 1191define signext i32 @setnbc30(double %a, double %b) { 1192; CHECK-LABEL: setnbc30: 1193; CHECK: # %bb.0: # %entry 1194; CHECK-NEXT: fcmpu cr0, f1, f2 1195; CHECK-NEXT: cror 4*cr5+lt, gt, un 1196; CHECK-NEXT: setnbc r3, 4*cr5+lt 1197; CHECK-NEXT: blr 1198entry: 1199 %cmp = fcmp ugt double %a, %b 1200 %conv = sext i1 %cmp to i32 1201 ret i32 %conv 1202} 1203 1204define signext i64 @setbc31(float %a, float %b) { 1205; CHECK-LABEL: setbc31: 1206; CHECK: # %bb.0: # %entry 1207; CHECK-NEXT: fcmpu cr0, f1, f2 1208; CHECK-NEXT: cror 4*cr5+lt, gt, un 1209; CHECK-NEXT: setbc r3, 4*cr5+lt 1210; CHECK-NEXT: blr 1211entry: 1212 %cmp = fcmp ugt float %a, %b 1213 %conv = zext i1 %cmp to i64 1214 ret i64 %conv 1215} 1216 1217define signext i64 @setnbc31(float %a, float %b) { 1218; CHECK-LABEL: setnbc31: 1219; CHECK: # %bb.0: # %entry 1220; CHECK-NEXT: fcmpu cr0, f1, f2 1221; CHECK-NEXT: cror 4*cr5+lt, gt, un 1222; CHECK-NEXT: setnbc r3, 4*cr5+lt 1223; CHECK-NEXT: blr 1224entry: 1225 %cmp = fcmp ugt float %a, %b 1226 %conv = sext i1 %cmp to i64 1227 ret i64 %conv 1228} 1229 1230define signext i64 @setbc32(double %a, double %b) { 1231; CHECK-LABEL: setbc32: 1232; CHECK: # %bb.0: # %entry 1233; CHECK-NEXT: fcmpu cr0, f1, f2 1234; CHECK-NEXT: cror 4*cr5+lt, gt, un 1235; CHECK-NEXT: setbc r3, 4*cr5+lt 1236; CHECK-NEXT: blr 1237entry: 1238 %cmp = fcmp ugt double %a, %b 1239 %conv = zext i1 %cmp to i64 1240 ret i64 %conv 1241} 1242 1243define signext i64 @setnbc32(double %a, double %b) { 1244; CHECK-LABEL: setnbc32: 1245; CHECK: # %bb.0: # %entry 1246; CHECK-NEXT: fcmpu cr0, f1, f2 1247; CHECK-NEXT: cror 4*cr5+lt, gt, un 1248; CHECK-NEXT: setnbc r3, 4*cr5+lt 1249; CHECK-NEXT: blr 1250entry: 1251 %cmp = fcmp ugt double %a, %b 1252 %conv = sext i1 %cmp to i64 1253 ret i64 %conv 1254} 1255 1256define signext i32 @setbc33(float %a, float %b) { 1257; CHECK-LABEL: setbc33: 1258; CHECK: # %bb.0: # %entry 1259; CHECK-NEXT: fcmpu cr0, f1, f2 1260; CHECK-NEXT: cror 4*cr5+lt, eq, un 1261; CHECK-NEXT: setbc r3, 4*cr5+lt 1262; CHECK-NEXT: blr 1263entry: 1264 %cmp = fcmp ueq float %a, %b 1265 %conv = zext i1 %cmp to i32 1266 ret i32 %conv 1267} 1268 1269define signext i32 @setnbc33(float %a, float %b) { 1270; CHECK-LABEL: setnbc33: 1271; CHECK: # %bb.0: # %entry 1272; CHECK-NEXT: fcmpu cr0, f1, f2 1273; CHECK-NEXT: cror 4*cr5+lt, eq, un 1274; CHECK-NEXT: setnbc r3, 4*cr5+lt 1275; CHECK-NEXT: blr 1276entry: 1277 %cmp = fcmp ueq float %a, %b 1278 %conv = sext i1 %cmp to i32 1279 ret i32 %conv 1280} 1281 1282define signext i32 @setbc34(double %a, double %b) { 1283; CHECK-LABEL: setbc34: 1284; CHECK: # %bb.0: # %entry 1285; CHECK-NEXT: fcmpu cr0, f1, f2 1286; CHECK-NEXT: cror 4*cr5+lt, eq, un 1287; CHECK-NEXT: setbc r3, 4*cr5+lt 1288; CHECK-NEXT: blr 1289entry: 1290 %cmp = fcmp ueq double %a, %b 1291 %conv = zext i1 %cmp to i32 1292 ret i32 %conv 1293} 1294 1295define signext i32 @setnbc34(double %a, double %b) { 1296; CHECK-LABEL: setnbc34: 1297; CHECK: # %bb.0: # %entry 1298; CHECK-NEXT: fcmpu cr0, f1, f2 1299; CHECK-NEXT: cror 4*cr5+lt, eq, un 1300; CHECK-NEXT: setnbc r3, 4*cr5+lt 1301; CHECK-NEXT: blr 1302entry: 1303 %cmp = fcmp ueq double %a, %b 1304 %conv = sext i1 %cmp to i32 1305 ret i32 %conv 1306} 1307 1308define signext i64 @setbc35(float %a, float %b) { 1309; CHECK-LABEL: setbc35: 1310; CHECK: # %bb.0: # %entry 1311; CHECK-NEXT: fcmpu cr0, f1, f2 1312; CHECK-NEXT: cror 4*cr5+lt, eq, un 1313; CHECK-NEXT: setbc r3, 4*cr5+lt 1314; CHECK-NEXT: blr 1315entry: 1316 %cmp = fcmp ueq float %a, %b 1317 %conv = zext i1 %cmp to i64 1318 ret i64 %conv 1319} 1320 1321define signext i64 @setnbc35(float %a, float %b) { 1322; CHECK-LABEL: setnbc35: 1323; CHECK: # %bb.0: # %entry 1324; CHECK-NEXT: fcmpu cr0, f1, f2 1325; CHECK-NEXT: cror 4*cr5+lt, eq, un 1326; CHECK-NEXT: setnbc r3, 4*cr5+lt 1327; CHECK-NEXT: blr 1328entry: 1329 %cmp = fcmp ueq float %a, %b 1330 %conv = sext i1 %cmp to i64 1331 ret i64 %conv 1332} 1333 1334define signext i64 @setbc36(double %a, double %b) { 1335; CHECK-LABEL: setbc36: 1336; CHECK: # %bb.0: # %entry 1337; CHECK-NEXT: fcmpu cr0, f1, f2 1338; CHECK-NEXT: cror 4*cr5+lt, eq, un 1339; CHECK-NEXT: setbc r3, 4*cr5+lt 1340; CHECK-NEXT: blr 1341entry: 1342 %cmp = fcmp ueq double %a, %b 1343 %conv = zext i1 %cmp to i64 1344 ret i64 %conv 1345} 1346 1347define signext i64 @setnbc36(double %a, double %b) { 1348; CHECK-LABEL: setnbc36: 1349; CHECK: # %bb.0: # %entry 1350; CHECK-NEXT: fcmpu cr0, f1, f2 1351; CHECK-NEXT: cror 4*cr5+lt, eq, un 1352; CHECK-NEXT: setnbc r3, 4*cr5+lt 1353; CHECK-NEXT: blr 1354entry: 1355 %cmp = fcmp ueq double %a, %b 1356 %conv = sext i1 %cmp to i64 1357 ret i64 %conv 1358} 1359 1360define signext i32 @setbc37(float %a, float %b) { 1361; CHECK-LABEL: setbc37: 1362; CHECK: # %bb.0: # %entry 1363; CHECK-NEXT: fcmpu cr0, f1, f2 1364; CHECK-NEXT: crnor 4*cr5+lt, un, eq 1365; CHECK-NEXT: setbc r3, 4*cr5+lt 1366; CHECK-NEXT: blr 1367entry: 1368 %cmp = fcmp one float %a, %b 1369 %conv = zext i1 %cmp to i32 1370 ret i32 %conv 1371} 1372 1373define signext i32 @setnbc37(float %a, float %b) { 1374; CHECK-LABEL: setnbc37: 1375; CHECK: # %bb.0: # %entry 1376; CHECK-NEXT: fcmpu cr0, f1, f2 1377; CHECK-NEXT: crnor 4*cr5+lt, un, eq 1378; CHECK-NEXT: setnbc r3, 4*cr5+lt 1379; CHECK-NEXT: blr 1380entry: 1381 %cmp = fcmp one float %a, %b 1382 %conv = sext i1 %cmp to i32 1383 ret i32 %conv 1384} 1385 1386define signext i32 @setbc38(double %a, double %b) { 1387; CHECK-LABEL: setbc38: 1388; CHECK: # %bb.0: # %entry 1389; CHECK-NEXT: fcmpu cr0, f1, f2 1390; CHECK-NEXT: crnor 4*cr5+lt, un, eq 1391; CHECK-NEXT: setbc r3, 4*cr5+lt 1392; CHECK-NEXT: blr 1393entry: 1394 %cmp = fcmp one double %a, %b 1395 %conv = zext i1 %cmp to i32 1396 ret i32 %conv 1397} 1398 1399define signext i32 @setnbc38(double %a, double %b) { 1400; CHECK-LABEL: setnbc38: 1401; CHECK: # %bb.0: # %entry 1402; CHECK-NEXT: fcmpu cr0, f1, f2 1403; CHECK-NEXT: crnor 4*cr5+lt, un, eq 1404; CHECK-NEXT: setnbc r3, 4*cr5+lt 1405; CHECK-NEXT: blr 1406entry: 1407 %cmp = fcmp one double %a, %b 1408 %conv = sext i1 %cmp to i32 1409 ret i32 %conv 1410} 1411 1412define signext i64 @setbc39(float %a, float %b) { 1413; CHECK-LABEL: setbc39: 1414; CHECK: # %bb.0: # %entry 1415; CHECK-NEXT: fcmpu cr0, f1, f2 1416; CHECK-NEXT: crnor 4*cr5+lt, un, eq 1417; CHECK-NEXT: setbc r3, 4*cr5+lt 1418; CHECK-NEXT: blr 1419entry: 1420 %cmp = fcmp one float %a, %b 1421 %conv = zext i1 %cmp to i64 1422 ret i64 %conv 1423} 1424 1425define signext i64 @setnbc39(float %a, float %b) { 1426; CHECK-LABEL: setnbc39: 1427; CHECK: # %bb.0: # %entry 1428; CHECK-NEXT: fcmpu cr0, f1, f2 1429; CHECK-NEXT: crnor 4*cr5+lt, un, eq 1430; CHECK-NEXT: setnbc r3, 4*cr5+lt 1431; CHECK-NEXT: blr 1432entry: 1433 %cmp = fcmp one float %a, %b 1434 %conv = sext i1 %cmp to i64 1435 ret i64 %conv 1436} 1437 1438define signext i64 @setbc40(double %a, double %b) { 1439; CHECK-LABEL: setbc40: 1440; CHECK: # %bb.0: # %entry 1441; CHECK-NEXT: fcmpu cr0, f1, f2 1442; CHECK-NEXT: crnor 4*cr5+lt, un, eq 1443; CHECK-NEXT: setbc r3, 4*cr5+lt 1444; CHECK-NEXT: blr 1445entry: 1446 %cmp = fcmp one double %a, %b 1447 %conv = zext i1 %cmp to i64 1448 ret i64 %conv 1449} 1450 1451define signext i64 @setnbc40(double %a, double %b) { 1452; CHECK-LABEL: setnbc40: 1453; CHECK: # %bb.0: # %entry 1454; CHECK-NEXT: fcmpu cr0, f1, f2 1455; CHECK-NEXT: crnor 4*cr5+lt, un, eq 1456; CHECK-NEXT: setnbc r3, 4*cr5+lt 1457; CHECK-NEXT: blr 1458entry: 1459 %cmp = fcmp one double %a, %b 1460 %conv = sext i1 %cmp to i64 1461 ret i64 %conv 1462} 1463