xref: /llvm-project/llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll (revision 5403c59c608c08c8ecd4303763f08eb046eb5e4d)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -S -passes='default<O3>' %s -o - | FileCheck %s
3define void @test_builtin_ppc_compare_and_swaplp(i64 %a, i64 %b, i64 %c) {
4; CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp(
5; CHECK-NEXT:  entry:
6; CHECK-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7; CHECK-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
8; CHECK-NEXT:    [[TMP0:%.*]] = cmpxchg weak volatile ptr [[A_ADDR]], i64 [[B:%.*]], i64 [[C:%.*]] monotonic monotonic, align 8
9; CHECK-NEXT:    ret void
10;
11entry:
12  %a.addr = alloca i64, align 8
13  %b.addr = alloca i64, align 8
14  %c.addr = alloca i64, align 8
15  store i64 %a, ptr %a.addr, align 8
16  store i64 %b, ptr %b.addr, align 8
17  store i64 %c, ptr %c.addr, align 8
18  %0 = load i64, ptr %c.addr, align 8
19  %1 = load i64, ptr %b.addr, align 8
20  %2 = cmpxchg weak volatile ptr %a.addr, i64 %1, i64 %0 monotonic monotonic, align 8
21  %3 = extractvalue { i64, i1 } %2, 0
22  %4 = extractvalue { i64, i1 } %2, 1
23  store i64 %3, ptr %b.addr, align 8
24  ret void
25}
26
27define dso_local void @test_builtin_ppc_compare_and_swaplp_loop(ptr %a) {
28; CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp_loop(
29; CHECK-NEXT:  entry:
30; CHECK-NEXT:    [[CALL:%.*]] = tail call i64 @bar()
31; CHECK-NEXT:    br label [[DO_BODY:%.*]]
32; CHECK:       do.body:
33; CHECK-NEXT:    [[X_0:%.*]] = phi i64 [ [[CALL]], [[ENTRY:%.*]] ], [ [[TMP1:%.*]], [[DO_BODY]] ]
34; CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[X_0]], 1
35; CHECK-NEXT:    [[TMP0:%.*]] = cmpxchg weak volatile ptr [[A:%.*]], i64 [[X_0]], i64 [[ADD]] monotonic monotonic, align 8
36; CHECK-NEXT:    [[TMP1]] = extractvalue { i64, i1 } [[TMP0]], 0
37; CHECK-NEXT:    [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
38; CHECK-NEXT:    br i1 [[TMP2]], label [[DO_BODY]], label [[DO_END:%.*]]
39; CHECK:       do.end:
40; CHECK-NEXT:    ret void
41;
42entry:
43  %a.addr = alloca ptr, align 8
44  %x = alloca i64, align 8
45  store ptr %a, ptr %a.addr, align 8
46  %call = call i64 @bar()
47  store i64 %call, ptr %x, align 8
48  br label %do.body
49
50do.body:                                          ; preds = %do.cond, %entry
51  br label %do.cond
52
53do.cond:                                          ; preds = %do.body
54  %0 = load ptr, ptr %a.addr, align 8
55  %1 = load i64, ptr %x, align 8
56  %add = add nsw i64 %1, 1
57  %2 = load ptr, ptr %a.addr, align 8
58  %3 = load i64, ptr %x, align 8
59  %4 = cmpxchg weak volatile ptr %2, i64 %3, i64 %add monotonic monotonic, align 8
60  %5 = extractvalue { i64, i1 } %4, 0
61  %6 = extractvalue { i64, i1 } %4, 1
62  store i64 %5, ptr %x, align 8
63  %tobool = icmp ne i1 %6, false
64  br i1 %tobool, label %do.body, label %do.end
65
66do.end:                                           ; preds = %do.cond
67  ret void
68}
69
70declare i64 @bar(...)
71