xref: /llvm-project/llvm/test/CodeGen/PowerPC/no-misaligned-tocl.ll (revision 19311e0a2e70c3775a67efe55780af65eb484b41)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
3; RUN:   -ppc-asm-full-reg-names -verify-machineinstrs < %s | FileCheck %s
4%0 = type <{ [7 x i8], i32, float, float, double, double, ppc_fp128 }>
5
6@var = external dso_local unnamed_addr global %0, align 16
7@ans = external dso_local unnamed_addr global i32, align 4
8
9define dso_local signext i32 @main() #0 {
10; CHECK-LABEL: main:
11; CHECK:       # %bb.0: # %bb
12; CHECK-NEXT:    addis r3, r2, var@toc@ha
13; CHECK-NEXT:    lis r4, 0
14; CHECK-NEXT:    lwz r3, var@toc@l+7(r3)
15; CHECK-NEXT:    ori r4, r4, 50000
16; CHECK-NEXT:    extsw r3, r3
17; CHECK-NEXT:    sub r3, r3, r4
18; CHECK-NEXT:    addis r4, r2, ans@toc@ha
19; CHECK-NEXT:    rldicl r3, r3, 1, 63
20; CHECK-NEXT:    stw r3, ans@toc@l(r4)
21bb:
22  %i = load i32, ptr getelementptr inbounds (%0, ptr @var, i64 0, i32 1), align 4
23  %i1 = icmp slt i32 %i, 50000
24  %i2 = zext i1 %i1 to i32
25  store i32 %i2, ptr @ans, align 4
26  unreachable
27}
28