1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s 3; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s 4 5define i64 @test1(i64 %x) { 6; CHECK-LABEL: test1: 7; CHECK: # %bb.0: 8; CHECK-NEXT: mulli 3, 3, 625 9; CHECK-NEXT: sldi 3, 3, 36 10; CHECK-NEXT: blr 11 %y = mul i64 %x, 42949672960000 12 ret i64 %y 13} 14 15define i64 @test2(i64 %x) { 16; CHECK-LABEL: test2: 17; CHECK: # %bb.0: 18; CHECK-NEXT: mulli 3, 3, -625 19; CHECK-NEXT: sldi 3, 3, 36 20; CHECK-NEXT: blr 21 %y = mul i64 %x, -42949672960000 22 ret i64 %y 23} 24 25define i64 @test3(i64 %x) { 26; CHECK-LABEL: test3: 27; CHECK: # %bb.0: 28; CHECK-NEXT: mulli 3, 3, 297 29; CHECK-NEXT: sldi 3, 3, 14 30; CHECK-NEXT: blr 31 %y = mul i64 %x, 4866048 32 ret i64 %y 33} 34 35define i64 @test4(i64 %x) { 36; CHECK-LABEL: test4: 37; CHECK: # %bb.0: 38; CHECK-NEXT: mulli 3, 3, -297 39; CHECK-NEXT: sldi 3, 3, 14 40; CHECK-NEXT: blr 41 %y = mul i64 %x, -4866048 42 ret i64 %y 43} 44 45define i64 @test5(i64 %x) { 46; CHECK-LABEL: test5: 47; CHECK: # %bb.0: 48; CHECK-NEXT: sldi 4, 3, 12 49; CHECK-NEXT: sldi 3, 3, 32 50; CHECK-NEXT: add 3, 3, 4 51; CHECK-NEXT: blr 52 %y = mul i64 %x, 4294971392 53 ret i64 %y 54} 55 56define i64 @test6(i64 %x) { 57; CHECK-LABEL: test6: 58; CHECK: # %bb.0: 59; CHECK-NEXT: sldi 4, 3, 12 60; CHECK-NEXT: sldi 3, 3, 32 61; CHECK-NEXT: add 3, 3, 4 62; CHECK-NEXT: neg 3, 3 63; CHECK-NEXT: blr 64 %y = mul i64 %x, -4294971392 65 ret i64 %y 66} 67 68define i64 @test7(i64 %x) { 69; CHECK-LABEL: test7: 70; CHECK: # %bb.0: 71; CHECK-NEXT: sldi 4, 3, 34 72; CHECK-NEXT: sldi 3, 3, 13 73; CHECK-NEXT: sub 3, 4, 3 74; CHECK-NEXT: blr 75 %y = mul i64 %x, 17179860992 76 ret i64 %y 77} 78 79define i64 @test8(i64 %x) { 80; CHECK-LABEL: test8: 81; CHECK: # %bb.0: 82; CHECK-NEXT: sldi 4, 3, 13 83; CHECK-NEXT: sldi 3, 3, 34 84; CHECK-NEXT: sub 3, 4, 3 85; CHECK-NEXT: blr 86 %y = mul i64 %x, -17179860992 87 ret i64 %y 88} 89 90define i64 @test9(i64 %x) { 91; CHECK-LABEL: test9: 92; CHECK: # %bb.0: 93; CHECK-NEXT: sldi 4, 3, 12 94; CHECK-NEXT: sldi 5, 3, 32 95; CHECK-NEXT: add 4, 5, 4 96; CHECK-NEXT: mulli 3, 3, 8193 97; CHECK-NEXT: sldi 3, 3, 19 98; CHECK-NEXT: sub 3, 4, 3 99; CHECK-NEXT: blr 100 %y = mul i64 %x, 4294971392 101 %z = mul i64 %x, 4295491584 102 %res = sub i64 %y, %z 103 ret i64 %res 104} 105 106define i64 @test10(i64 %x) { 107; CHECK-LABEL: test10: 108; CHECK: # %bb.0: 109; CHECK-NEXT: sldi 4, 3, 34 110; CHECK-NEXT: sldi 3, 3, 30 111; CHECK-NEXT: sub 3, 4, 3 112; CHECK-NEXT: blr 113 %y = mul i64 %x, 17179860992 114 %z = mul i64 %x, 1073733632 115 %res = sub i64 %y, %z 116 ret i64 %res 117} 118 119define i32 @test11(i32 %x) { 120; CHECK-LABEL: test11: 121; CHECK: # %bb.0: 122; CHECK-NEXT: mulli 3, 3, 21845 123; CHECK-NEXT: slwi 3, 3, 5 124; CHECK-NEXT: blr 125 %y = mul nsw i32 %x, 699040 126 ret i32 %y 127} 128