1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ 3; RUN: -mcpu=pwr8 -O2 < %s | FileCheck %s 4 5define void @test_mtvscr() { 6; CHECK-LABEL: test_mtvscr: 7; CHECK: # %bb.0: # %test_mtvscr_entry 8; CHECK-NEXT: addi 3, 1, -16 9; CHECK-NEXT: lxvd2x 0, 0, 3 10; CHECK-NEXT: xxswapd 34, 0 11; CHECK-NEXT: mtvscr 2 12; CHECK-NEXT: blr 13test_mtvscr_entry: 14 %0 = alloca <4 x i32> 15 %1 = load <4 x i32>, ptr %0 16 call void @llvm.ppc.altivec.mtvscr(<4 x i32> %1) 17 ret void 18} 19 20define void @test_mfvscr() { 21; CHECK-LABEL: test_mfvscr: 22; CHECK: # %bb.0: # %test_mfvscr_entry 23; CHECK-NEXT: mfvscr 2 24; CHECK-NEXT: addi 3, 1, -16 25; CHECK-NEXT: xxswapd 0, 34 26; CHECK-NEXT: stxvd2x 0, 0, 3 27; CHECK-NEXT: blr 28test_mfvscr_entry: 29 %0 = alloca <8 x i16> 30 %1 = call <8 x i16> @llvm.ppc.altivec.mfvscr() 31 store <8 x i16> %1, ptr %0 32 ret void 33} 34 35declare void @llvm.ppc.altivec.mtvscr(<4 x i32>) 36 37declare <8 x i16> @llvm.ppc.altivec.mfvscr() 38