1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; This test is a copy of mma-acc-spill.ll except that it uses mcpu=future. 3; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 4; RUN: -disable-auto-paired-vec-st=false \ 5; RUN: -mcpu=future -ppc-asm-full-reg-names \ 6; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s 7; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 8; RUN: -disable-auto-paired-vec-st=false \ 9; RUN: -mcpu=future -ppc-asm-full-reg-names \ 10; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE 11 12declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>) 13declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) 14declare void @foo() 15define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, ptr %ptr) { 16; CHECK-LABEL: intrinsics1: 17; CHECK: # %bb.0: 18; CHECK-NEXT: mflr r0 19; CHECK-NEXT: std r0, 16(r1) 20; CHECK-NEXT: stdu r1, -176(r1) 21; CHECK-NEXT: .cfi_def_cfa_offset 176 22; CHECK-NEXT: .cfi_offset lr, 16 23; CHECK-NEXT: .cfi_offset r30, -16 24; CHECK-NEXT: .cfi_offset v28, -80 25; CHECK-NEXT: .cfi_offset v29, -64 26; CHECK-NEXT: .cfi_offset v30, -48 27; CHECK-NEXT: .cfi_offset v31, -32 28; CHECK-NEXT: stxv v28, 96(r1) # 16-byte Folded Spill 29; CHECK-NEXT: stxv v29, 112(r1) # 16-byte Folded Spill 30; CHECK-NEXT: stxv v30, 128(r1) # 16-byte Folded Spill 31; CHECK-NEXT: stxv v31, 144(r1) # 16-byte Folded Spill 32; CHECK-NEXT: vmr v31, v5 33; CHECK-NEXT: vmr v29, v3 34; CHECK-NEXT: vmr v30, v4 35; CHECK-NEXT: vmr v28, v2 36; CHECK-NEXT: std r30, 160(r1) # 8-byte Folded Spill 37; CHECK-NEXT: ld r30, 272(r1) 38; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0 39; CHECK-NEXT: xvf16ger2pp wacc0, v2, v4 40; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp36, vsp34, 0 41; CHECK-NEXT: stxvp vsp36, 64(r1) 42; CHECK-NEXT: stxvp vsp34, 32(r1) 43; CHECK-NEXT: bl foo@notoc 44; CHECK-NEXT: lxvp vsp34, 64(r1) 45; CHECK-NEXT: lxvp vsp36, 32(r1) 46; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0 47; CHECK-NEXT: xvf16ger2pp wacc0, v28, v30 48; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0 49; CHECK-NEXT: stxv v4, 48(r30) 50; CHECK-NEXT: stxv v5, 32(r30) 51; CHECK-NEXT: stxv v2, 16(r30) 52; CHECK-NEXT: stxv v3, 0(r30) 53; CHECK-NEXT: lxv v31, 144(r1) # 16-byte Folded Reload 54; CHECK-NEXT: lxv v30, 128(r1) # 16-byte Folded Reload 55; CHECK-NEXT: lxv v29, 112(r1) # 16-byte Folded Reload 56; CHECK-NEXT: lxv v28, 96(r1) # 16-byte Folded Reload 57; CHECK-NEXT: ld r30, 160(r1) # 8-byte Folded Reload 58; CHECK-NEXT: addi r1, r1, 176 59; CHECK-NEXT: ld r0, 16(r1) 60; CHECK-NEXT: mtlr r0 61; CHECK-NEXT: blr 62; 63; CHECK-BE-LABEL: intrinsics1: 64; CHECK-BE: # %bb.0: 65; CHECK-BE-NEXT: mflr r0 66; CHECK-BE-NEXT: std r0, 16(r1) 67; CHECK-BE-NEXT: stdu r1, -256(r1) 68; CHECK-BE-NEXT: .cfi_def_cfa_offset 256 69; CHECK-BE-NEXT: .cfi_offset lr, 16 70; CHECK-BE-NEXT: .cfi_offset r30, -16 71; CHECK-BE-NEXT: .cfi_offset v28, -80 72; CHECK-BE-NEXT: .cfi_offset v29, -64 73; CHECK-BE-NEXT: .cfi_offset v30, -48 74; CHECK-BE-NEXT: .cfi_offset v31, -32 75; CHECK-BE-NEXT: stxv v28, 176(r1) # 16-byte Folded Spill 76; CHECK-BE-NEXT: stxv v29, 192(r1) # 16-byte Folded Spill 77; CHECK-BE-NEXT: stxv v30, 208(r1) # 16-byte Folded Spill 78; CHECK-BE-NEXT: stxv v31, 224(r1) # 16-byte Folded Spill 79; CHECK-BE-NEXT: vmr v31, v5 80; CHECK-BE-NEXT: vmr v29, v3 81; CHECK-BE-NEXT: vmr v30, v4 82; CHECK-BE-NEXT: vmr v28, v2 83; CHECK-BE-NEXT: std r30, 240(r1) # 8-byte Folded Spill 84; CHECK-BE-NEXT: ld r30, 368(r1) 85; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0 86; CHECK-BE-NEXT: xvf16ger2pp wacc0, v2, v4 87; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp36, vsp34, 0 88; CHECK-BE-NEXT: stxvp vsp36, 112(r1) 89; CHECK-BE-NEXT: stxvp vsp34, 144(r1) 90; CHECK-BE-NEXT: bl foo 91; CHECK-BE-NEXT: nop 92; CHECK-BE-NEXT: lxvp vsp34, 112(r1) 93; CHECK-BE-NEXT: lxvp vsp36, 144(r1) 94; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0 95; CHECK-BE-NEXT: xvf16ger2pp wacc0, v28, v30 96; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0 97; CHECK-BE-NEXT: stxv v5, 48(r30) 98; CHECK-BE-NEXT: stxv v4, 32(r30) 99; CHECK-BE-NEXT: stxv v3, 16(r30) 100; CHECK-BE-NEXT: stxv v2, 0(r30) 101; CHECK-BE-NEXT: lxv v31, 224(r1) # 16-byte Folded Reload 102; CHECK-BE-NEXT: lxv v30, 208(r1) # 16-byte Folded Reload 103; CHECK-BE-NEXT: lxv v29, 192(r1) # 16-byte Folded Reload 104; CHECK-BE-NEXT: lxv v28, 176(r1) # 16-byte Folded Reload 105; CHECK-BE-NEXT: ld r30, 240(r1) # 8-byte Folded Reload 106; CHECK-BE-NEXT: addi r1, r1, 256 107; CHECK-BE-NEXT: ld r0, 16(r1) 108; CHECK-BE-NEXT: mtlr r0 109; CHECK-BE-NEXT: blr 110 %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4) 111 %2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc3) 112 tail call void @foo() 113 %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3) 114 store <512 x i1> %3, ptr %ptr, align 64 115 ret void 116} 117