xref: /llvm-project/llvm/test/CodeGen/PowerPC/memcmpIR.ll (revision 4dfea22e771a0944b3b313f2790a616fa79257e1)
1; RUN: llc -o - -mtriple=powerpc64le-unknown-gnu-linux -stop-after codegenprepare %s | FileCheck %s
2; RUN: llc -o - -mtriple=powerpc64-unknown-gnu-linux -stop-after codegenprepare %s | FileCheck %s --check-prefix=CHECK-BE
3
4define signext i32 @test1(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2)  {
5entry:
6  ; CHECK-LABEL: @test1(
7  ; CHECK-LABEL: res_block:{{.*}}
8  ; CHECK: [[ICMP2:%[0-9]+]] = icmp ult i64
9  ; CHECK-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
10  ; CHECK-NEXT: br label %endblock
11
12  ; CHECK-LABEL: loadbb:{{.*}}
13  ; CHECK: [[LOAD1:%[0-9]+]] = load i64, ptr
14  ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr
15  ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD1]])
16  ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD2]])
17  ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[BSWAP1]], [[BSWAP2]]
18  ; CHECK-NEXT:  br i1 [[ICMP]], label %loadbb1, label %res_block
19
20  ; CHECK-LABEL: loadbb1:{{.*}}
21  ; CHECK-NEXT: [[GEP1:%[0-9]+]] = getelementptr i8, ptr {{.*}}, i64 8
22  ; CHECK-NEXT: [[GEP2:%[0-9]+]] = getelementptr i8, ptr {{.*}}, i64 8
23  ; CHECK-NEXT: [[LOAD1:%[0-9]+]] = load i64, ptr [[GEP1]]
24  ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr [[GEP2]]
25  ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD1]])
26  ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD2]])
27  ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[BSWAP1]], [[BSWAP2]]
28  ; CHECK-NEXT:  br i1 [[ICMP]], label %endblock, label %res_block
29
30  ; CHECK-BE-LABEL: @test1(
31  ; CHECK-BE-LABEL: res_block:{{.*}}
32  ; CHECK-BE: [[ICMP2:%[0-9]+]] = icmp ult i64
33  ; CHECK-BE-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
34  ; CHECK-BE-NEXT: br label %endblock
35
36  ; CHECK-BE-LABEL: loadbb:{{.*}}
37  ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i64, ptr
38  ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr
39  ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[LOAD1]], [[LOAD2]]
40  ; CHECK-BE-NEXT:  br i1 [[ICMP]], label %loadbb1, label %res_block
41
42  ; CHECK-BE-LABEL: loadbb1:{{.*}}
43  ; CHECK-BE-NEXT: [[GEP1:%[0-9]+]] = getelementptr i8, ptr {{.*}}, i64 8
44  ; CHECK-BE-NEXT: [[GEP2:%[0-9]+]] = getelementptr i8, ptr {{.*}}, i64 8
45  ; CHECK-BE-NEXT: [[LOAD1:%[0-9]+]] = load i64, ptr [[GEP1]]
46  ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr [[GEP2]]
47  ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[LOAD1]], [[LOAD2]]
48  ; CHECK-BE-NEXT:  br i1 [[ICMP]], label %endblock, label %res_block
49
50  %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 16)
51  ret i32 %call
52}
53
54declare signext i32 @memcmp(ptr nocapture, ptr nocapture, i64) local_unnamed_addr #1
55
56define signext i32 @test2(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2)  {
57  ; CHECK-LABEL: @test2(
58  ; CHECK: [[LOAD1:%[0-9]+]] = load i32, ptr
59  ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i32, ptr
60  ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD1]])
61  ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD2]])
62  ; CHECK-NEXT: [[UCMP:%[0-9]+]] = call i32 @llvm.ucmp.i32.i32(i32 [[BSWAP1]], i32 [[BSWAP2]])
63  ; CHECK-NEXT: ret i32 [[UCMP]]
64
65  ; CHECK-BE-LABEL: @test2(
66  ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i32, ptr
67  ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i32, ptr
68  ; CHECK-BE-NEXT: [[UCMP:%[0-9]+]] = call i32 @llvm.ucmp.i32.i32(i32 [[LOAD1]], i32 [[LOAD2]])
69  ; CHECK-BE-NEXT: ret i32 [[UCMP]]
70
71entry:
72  %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 4)
73  ret i32 %call
74}
75
76define signext i32 @test3(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2)  {
77  ; CHECK-LABEL: res_block:{{.*}}
78  ; CHECK: [[ICMP2:%[0-9]+]] = icmp ult i64
79  ; CHECK-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
80  ; CHECK-NEXT: br label %endblock
81
82  ; CHECK-LABEL: loadbb:{{.*}}
83  ; CHECK: [[LOAD1:%[0-9]+]] = load i64, ptr
84  ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr
85  ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD1]])
86  ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD2]])
87  ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[BSWAP1]], [[BSWAP2]]
88  ; CHECK-NEXT:  br i1 [[ICMP]], label %loadbb1, label %res_block
89
90  ; CHECK-LABEL: loadbb1:{{.*}}
91  ; CHECK: [[LOAD1:%[0-9]+]] = load i32, ptr
92  ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i32, ptr
93  ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD1]])
94  ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD2]])
95  ; CHECK-NEXT: [[ZEXT1:%[0-9]+]] = zext i32 [[BSWAP1]] to i64
96  ; CHECK-NEXT: [[ZEXT2:%[0-9]+]] = zext i32 [[BSWAP2]] to i64
97  ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[ZEXT1]], [[ZEXT2]]
98  ; CHECK-NEXT:  br i1 [[ICMP]], label %loadbb2, label %res_block
99
100  ; CHECK-LABEL: loadbb2:{{.*}}
101  ; CHECK: [[LOAD1:%[0-9]+]] = load i16, ptr
102  ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i16, ptr
103  ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i16 @llvm.bswap.i16(i16 [[LOAD1]])
104  ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i16 @llvm.bswap.i16(i16 [[LOAD2]])
105  ; CHECK-NEXT: [[ZEXT1:%[0-9]+]] = zext i16 [[BSWAP1]] to i64
106  ; CHECK-NEXT: [[ZEXT2:%[0-9]+]] = zext i16 [[BSWAP2]] to i64
107  ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[ZEXT1]], [[ZEXT2]]
108  ; CHECK-NEXT:  br i1 [[ICMP]], label %loadbb3, label %res_block
109
110  ; CHECK-LABEL: loadbb3:{{.*}}
111  ; CHECK: [[LOAD1:%[0-9]+]] = load i8, ptr
112  ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i8, ptr
113  ; CHECK-NEXT: [[ZEXT1:%[0-9]+]] = zext i8 [[LOAD1]] to i32
114  ; CHECK-NEXT: [[ZEXT2:%[0-9]+]] = zext i8 [[LOAD2]] to i32
115  ; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i32 [[ZEXT1]], [[ZEXT2]]
116  ; CHECK-NEXT:  br label %endblock
117
118  ; CHECK-BE-LABEL: res_block:{{.*}}
119  ; CHECK-BE: [[ICMP2:%[0-9]+]] = icmp ult i64
120  ; CHECK-BE-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
121  ; CHECK-BE-NEXT: br label %endblock
122
123  ; CHECK-BE-LABEL: loadbb:{{.*}}
124  ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i64, ptr
125  ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr
126  ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[LOAD1]], [[LOAD2]]
127  ; CHECK-BE-NEXT:  br i1 [[ICMP]], label %loadbb1, label %res_block
128
129  ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i32, ptr
130  ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i32, ptr
131  ; CHECK-BE-NEXT: [[ZEXT1:%[0-9]+]] = zext i32 [[LOAD1]] to i64
132  ; CHECK-BE-NEXT: [[ZEXT2:%[0-9]+]] = zext i32 [[LOAD2]] to i64
133  ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[ZEXT1]], [[ZEXT2]]
134  ; CHECK-BE-NEXT:  br i1 [[ICMP]], label %loadbb2, label %res_block
135
136  ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i16, ptr
137  ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i16, ptr
138  ; CHECK-BE-NEXT: [[ZEXT1:%[0-9]+]] = zext i16 [[LOAD1]] to i64
139  ; CHECK-BE-NEXT: [[ZEXT2:%[0-9]+]] = zext i16 [[LOAD2]] to i64
140  ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[ZEXT1]], [[ZEXT2]]
141  ; CHECK-BE-NEXT:  br i1 [[ICMP]], label %loadbb3, label %res_block
142
143  ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i8, ptr
144  ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i8, ptr
145  ; CHECK-BE-NEXT: [[ZEXT1:%[0-9]+]] = zext i8 [[LOAD1]] to i32
146  ; CHECK-BE-NEXT: [[ZEXT2:%[0-9]+]] = zext i8 [[LOAD2]] to i32
147  ; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i32 [[ZEXT1]], [[ZEXT2]]
148  ; CHECK-BE-NEXT:  br label %endblock
149
150entry:
151  %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 15)
152  ret i32 %call
153}
154  ; CHECK: call = tail call signext i32 @memcmp
155  ; CHECK-BE: call = tail call signext i32 @memcmp
156define signext i32 @test4(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2)  {
157
158entry:
159  %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 65)
160  ret i32 %call
161}
162
163define signext i32 @test5(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2, i32 signext %SIZE)  {
164  ; CHECK: call = tail call signext i32 @memcmp
165  ; CHECK-BE: call = tail call signext i32 @memcmp
166entry:
167  %conv = sext i32 %SIZE to i64
168  %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 %conv)
169  ret i32 %call
170}
171