xref: /llvm-project/llvm/test/CodeGen/PowerPC/lower-massv.ll (revision 45951ad3231c213e7fae384dc9ce803bfaed8c77)
1; RUN: llc -verify-machineinstrs -mcpu=pwr10  < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR9,CHECK-ALL %s
2; RUN: llc -verify-machineinstrs -mcpu=pwr9   < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR9,CHECK-ALL %s
3; RUN: llc -verify-machineinstrs -mcpu=pwr8   < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR8,CHECK-ALL %s
4; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR8,CHECK-ALL %s
5; RUN: llc -verify-machineinstrs -mcpu=pwr10  < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR10,CHECK-ALL %s
6; RUN: llc -verify-machineinstrs -mcpu=pwr9   < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR9,CHECK-ALL %s
7; RUN: llc -verify-machineinstrs -mcpu=pwr8   < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR8,CHECK-ALL %s
8; RUN: llc -verify-machineinstrs -mcpu=pwr7   < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR7,CHECK-ALL %s
9; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR7,CHECK-ALL %s
10
11declare <2 x double> @__cbrtd2(<2 x double>)
12declare <4 x float> @__cbrtf4(<4 x float>)
13
14declare <2 x double> @__powd2(<2 x double>, <2 x double>)
15declare <4 x float> @__powf4(<4 x float>, <4 x float>)
16
17declare <2 x double> @__expd2(<2 x double>)
18declare <4 x float> @__expf4(<4 x float>)
19
20declare <2 x double> @__exp2d2(<2 x double>)
21declare <4 x float> @__exp2f4(<4 x float>)
22
23declare <2 x double> @__expm1d2(<2 x double>)
24declare <4 x float> @__expm1f4(<4 x float>)
25
26declare <2 x double> @__logd2(<2 x double>)
27declare <4 x float> @__logf4(<4 x float>)
28
29declare <2 x double> @__log1pd2(<2 x double>)
30declare <4 x float> @__log1pf4(<4 x float>)
31
32declare <2 x double> @__log10d2(<2 x double>)
33declare <4 x float> @__log10f4(<4 x float>)
34
35declare <2 x double> @__log2d2(<2 x double>)
36declare <4 x float> @__log2f4(<4 x float>)
37
38declare <2 x double> @__sind2(<2 x double>)
39declare <4 x float> @__sinf4(<4 x float>)
40
41declare <2 x double> @__cosd2(<2 x double>)
42declare <4 x float> @__cosf4(<4 x float>)
43
44declare <2 x double> @__tand2(<2 x double>)
45declare <4 x float> @__tanf4(<4 x float>)
46
47declare <2 x double> @__asind2(<2 x double>)
48declare <4 x float> @__asinf4(<4 x float>)
49
50declare <2 x double> @__acosd2(<2 x double>)
51declare <4 x float> @__acosf4(<4 x float>)
52
53declare <2 x double> @__atand2(<2 x double>)
54declare <4 x float> @__atanf4(<4 x float>)
55
56declare <2 x double> @__atan2d2(<2 x double>)
57declare <4 x float> @__atan2f4(<4 x float>)
58
59declare <2 x double> @__sinhd2(<2 x double>)
60declare <4 x float> @__sinhf4(<4 x float>)
61
62declare <2 x double> @__coshd2(<2 x double>)
63declare <4 x float> @__coshf4(<4 x float>)
64
65declare <2 x double> @__tanhd2(<2 x double>)
66declare <4 x float> @__tanhf4(<4 x float>)
67
68declare <2 x double> @__asinhd2(<2 x double>)
69declare <4 x float> @__asinhf4(<4 x float>)
70
71declare <2 x double> @__acoshd2(<2 x double>)
72declare <4 x float> @__acoshf4(<4 x float>)
73
74declare <2 x double> @__atanhd2(<2 x double>)
75declare <4 x float> @__atanhf4(<4 x float>)
76
77; following tests check generation of subtarget-specific calls
78; cbrt
79define <2 x double>  @cbrt_f64_massv(<2 x double> %opnd) {
80; CHECK-ALL-LABEL: @cbrt_f64_massv
81; CHECK-PWR10: __cbrtd2_P10
82; CHECK-PWR9:  __cbrtd2_P9
83; CHECK-PWR8:  __cbrtd2_P8
84; CHECK-PWR7:  __cbrtd2_P7
85; CHECK-NOT:   __cbrtd2_massv
86; CHECK-ALL:   blr
87;
88  %1 = call <2 x double> @__cbrtd2(<2 x double> %opnd)
89  ret <2 x double> %1
90}
91
92define <4 x float>  @cbrt_f32_massv(<4 x float> %opnd) {
93; CHECK-ALL-LABEL: @cbrt_f32_massv
94; CHECK-PWR10: __cbrtf4_P10
95; CHECK-PWR9:  __cbrtf4_P9
96; CHECK-PWR8:  __cbrtf4_P8
97; CHECK-PWR7:  __cbrtf4_P7
98; CHECK-NOT:   __cbrtf4_massv
99; CHECK-ALL:   blr
100;
101  %1 = call <4 x float> @__cbrtf4(<4 x float> %opnd)
102  ret <4 x float> %1
103}
104
105; pow
106define <2 x double>  @pow_f64_massv(<2 x double> %opnd1, <2 x double> %opnd2) {
107; CHECK-ALL-LABEL: @pow_f64_massv
108; CHECK-PWR10: __powd2_P10
109; CHECK-PWR9:  __powd2_P9
110; CHECK-PWR8:  __powd2_P8
111; CHECK-PWR7:  __powd2_P7
112; CHECK-NOT:   __powd2_massv
113; CHECK-ALL:   blr
114;
115 %1 = call <2 x double> @__powd2(<2 x double> %opnd1, <2 x double> %opnd2)
116  ret <2 x double> %1
117}
118
119define <4 x float>  @pow_f32_massv(<4 x float> %opnd1, <4 x float> %opnd2) {
120; CHECK-ALL-LABEL: @pow_f32_massv
121; CHECK-PWR10: __powf4_P10
122; CHECK-PWR9:  __powf4_P9
123; CHECK-PWR8:  __powf4_P8
124; CHECK-PWR7:  __powf4_P7
125; CHECK-NOT:   __powf4_massv
126; CHECK-ALL:   blr
127;
128 %1 = call <4 x float> @__powf4(<4 x float> %opnd1, <4 x float> %opnd2)
129  ret <4 x float> %1
130}
131
132; exp
133define <2 x double>  @exp_f64_massv(<2 x double> %opnd) {
134; CHECK-ALL-LABEL: @exp_f64_massv
135; CHECK-PWR10: __expd2_P10
136; CHECK-PWR9:  __expd2_P9
137; CHECK-PWR8:  __expd2_P8
138; CHECK-PWR7:  __expd2_P7
139; CHECK-NOT:   __expd2_massv
140; CHECK-ALL:   blr
141;
142  %1 = call <2 x double> @__expd2(<2 x double> %opnd)
143  ret <2 x double> %1
144}
145
146define <4 x float>  @exp_f32_massv(<4 x float> %opnd) {
147; CHECK-ALL-LABEL: @exp_f32_massv
148; CHECK-PWR10: __expf4_P10
149; CHECK-PWR9:  __expf4_P9
150; CHECK-PWR8:  __expf4_P8
151; CHECK-PWR7:  __expf4_P7
152; CHECK-NOT:   __expf4_massv
153; CHECK-ALL:   blr
154;
155  %1 = call <4 x float> @__expf4(<4 x float> %opnd)
156  ret <4 x float> %1
157}
158
159; exp2
160define <2 x double>  @exp2_f64_massv(<2 x double> %opnd) {
161; CHECK-ALL-LABEL: @exp2_f64_massv
162; CHECK-PWR10: __exp2d2_P10
163; CHECK-PWR9:  __exp2d2_P9
164; CHECK-PWR8:  __exp2d2_P8
165; CHECK-PWR7:  __exp2d2_P7
166; CHECK-NOT:   __exp2d2_massv
167; CHECK-ALL:   blr
168;
169  %1 = call <2 x double> @__exp2d2(<2 x double> %opnd)
170  ret <2 x double> %1
171}
172
173define <4 x float>  @exp2_f32_massv(<4 x float> %opnd) {
174; CHECK-ALL-LABEL: @exp2_f32_massv
175; CHECK-PWR10: __exp2f4_P10
176; CHECK-PWR9:  __exp2f4_P9
177; CHECK-PWR8:  __exp2f4_P8
178; CHECK-PWR7:  __exp2f4_P7
179; CHECK-NOT:   __exp2f4_massv
180; CHECK-ALL:   blr
181;
182  %1 = call <4 x float> @__exp2f4(<4 x float> %opnd)
183  ret <4 x float> %1
184}
185
186; expm1
187define <2 x double>  @expm1_f64_massv(<2 x double> %opnd) {
188; CHECK-ALL-LABEL: @expm1_f64_massv
189; CHECK-PWR10: __expm1d2_P10
190; CHECK-PWR9:  __expm1d2_P9
191; CHECK-PWR8:  __expm1d2_P8
192; CHECK-PWR7:  __expm1d2_P7
193; CHECK-NOT:   __expm1d2_massv
194; CHECK-ALL:   blr
195;
196  %1 = call <2 x double> @__expm1d2(<2 x double> %opnd)
197  ret <2 x double> %1
198}
199
200define <4 x float>  @expm1_f32_massv(<4 x float> %opnd) {
201; CHECK-ALL-LABEL: @expm1_f32_massv
202; CHECK-PWR10: __expm1f4_P10
203; CHECK-PWR9:  __expm1f4_P9
204; CHECK-PWR8:  __expm1f4_P8
205; CHECK-PWR7:  __expm1f4_P7
206; CHECK-NOT:   __expm1f4_massv
207; CHECK-ALL:   blr
208;
209  %1 = call <4 x float> @__expm1f4(<4 x float> %opnd)
210  ret <4 x float> %1
211}
212
213; log
214define <2 x double>  @log_f64_massv(<2 x double> %opnd) {
215; CHECK-ALL-LABEL: @log_f64_massv
216; CHECK-PWR10: __logd2_P10
217; CHECK-PWR9:  __logd2_P9
218; CHECK-PWR8:  __logd2_P8
219; CHECK-PWR7:  __logd2_P7
220; CHECK-NOT:   __logd2_massv
221; CHECK-ALL:   blr
222;
223  %1 = call <2 x double> @__logd2(<2 x double> %opnd)
224  ret <2 x double> %1
225}
226
227define <4 x float>  @log_f32_massv(<4 x float> %opnd) {
228; CHECK-ALL-LABEL: @log_f32_massv
229; CHECK-PWR10: __logf4_P10
230; CHECK-PWR9:  __logf4_P9
231; CHECK-PWR8:  __logf4_P8
232; CHECK-PWR7:  __logf4_P7
233; CHECK-NOT:   __logf4_massv
234; CHECK-ALL:   blr
235;
236  %1 = call <4 x float> @__logf4(<4 x float> %opnd)
237  ret <4 x float> %1
238}
239
240; log1p
241define <2 x double>  @log1p_f64_massv(<2 x double> %opnd) {
242; CHECK-ALL-LABEL: @log1p_f64_massv
243; CHECK-PWR10: __log1pd2_P10
244; CHECK-PWR9:  __log1pd2_P9
245; CHECK-PWR8:  __log1pd2_P8
246; CHECK-PWR7:  __log1pd2_P7
247; CHECK-NOT:   __log1pd2_massv
248; CHECK-ALL:   blr
249;
250  %1 = call <2 x double> @__log1pd2(<2 x double> %opnd)
251  ret <2 x double> %1
252}
253
254define <4 x float>  @log1p_f32_massv(<4 x float> %opnd) {
255; CHECK-ALL-LABEL: @log1p_f32_massv
256; CHECK-PWR10: __log1pf4_P10
257; CHECK-PWR9:  __log1pf4_P9
258; CHECK-PWR8:  __log1pf4_P8
259; CHECK-PWR7:  __log1pf4_P7
260; CHECK-NOT:   __log1pf4_massv
261; CHECK-ALL:   blr
262;
263  %1 = call <4 x float> @__log1pf4(<4 x float> %opnd)
264  ret <4 x float> %1
265}
266
267; log10
268define <2 x double>  @log10_f64_massv(<2 x double> %opnd) {
269; CHECK-ALL-LABEL: @log10_f64_massv
270; CHECK-PWR10: __log10d2_P10
271; CHECK-PWR9:  __log10d2_P9
272; CHECK-PWR8:  __log10d2_P8
273; CHECK-PWR7:  __log10d2_P7
274; CHECK-NOT:   __log10d2_massv
275; CHECK-ALL:   blr
276;
277  %1 = call <2 x double> @__log10d2(<2 x double> %opnd)
278  ret <2 x double> %1
279}
280
281define <4 x float>  @log10_f32_massv(<4 x float> %opnd) {
282; CHECK-ALL-LABEL: @log10_f32_massv
283; CHECK-PWR10: __log10f4_P10
284; CHECK-PWR9:  __log10f4_P9
285; CHECK-PWR8:  __log10f4_P8
286; CHECK-PWR7:  __log10f4_P7
287; CHECK-NOT:   __log10f4_massv
288; CHECK-ALL:   blr
289;
290  %1 = call <4 x float> @__log10f4(<4 x float> %opnd)
291  ret <4 x float> %1
292}
293
294; log2
295define <2 x double>  @log2_f64_massv(<2 x double> %opnd) {
296; CHECK-ALL-LABEL: @log2_f64_massv
297; CHECK-PWR10: __log2d2_P10
298; CHECK-PWR9:  __log2d2_P9
299; CHECK-PWR8:  __log2d2_P8
300; CHECK-PWR7:  __log2d2_P7
301; CHECK-NOT:   __log2d2_massv
302; CHECK-ALL:   blr
303;
304  %1 = call <2 x double> @__log2d2(<2 x double> %opnd)
305  ret <2 x double> %1
306}
307
308define <4 x float>  @log2_f32_massv(<4 x float> %opnd) {
309; CHECK-ALL-LABEL: @log2_f32_massv
310; CHECK-PWR10: __log2f4_P10
311; CHECK-PWR9:  __log2f4_P9
312; CHECK-PWR8:  __log2f4_P8
313; CHECK-PWR7:  __log2f4_P7
314; CHECK-NOT:   __log2f4_massv
315; CHECK-ALL:   blr
316;
317  %1 = call <4 x float> @__log2f4(<4 x float> %opnd)
318  ret <4 x float> %1
319}
320
321; sin
322define <2 x double>  @sin_f64_massv(<2 x double> %opnd) {
323; CHECK-ALL-LABEL: @sin_f64_massv
324; CHECK-PWR10: __sind2_P10
325; CHECK-PWR9:  __sind2_P9
326; CHECK-PWR8:  __sind2_P8
327; CHECK-PWR7:  __sind2_P7
328; CHECK-NOT:   __sind2_massv
329; CHECK-ALL:   blr
330;
331  %1 = call <2 x double> @__sind2(<2 x double> %opnd)
332  ret <2 x double> %1
333}
334
335define <4 x float>  @sin_f32_massv(<4 x float> %opnd) {
336; CHECK-ALL-LABEL: @sin_f32_massv
337; CHECK-PWR10: __sinf4_P10
338; CHECK-PWR9:  __sinf4_P9
339; CHECK-PWR8:  __sinf4_P8
340; CHECK-PWR7:  __sinf4_P7
341; CHECK-NOT:   __sinf4_massv
342; CHECK-ALL:   blr
343;
344  %1 = call <4 x float> @__sinf4(<4 x float> %opnd)
345  ret <4 x float> %1
346}
347
348; cos
349define <2 x double>  @cos_f64_massv(<2 x double> %opnd) {
350; CHECK-ALL-LABEL: @cos_f64_massv
351; CHECK-PWR10: __cosd2_P10
352; CHECK-PWR9:  __cosd2_P9
353; CHECK-PWR8:  __cosd2_P8
354; CHECK-PWR7:  __cosd2_P7
355; CHECK-NOT:   __cosd2_massv
356; CHECK-ALL:   blr
357;
358  %1 = call <2 x double> @__cosd2(<2 x double> %opnd)
359  ret <2 x double> %1
360}
361
362define <4 x float>  @cos_f32_massv(<4 x float> %opnd) {
363; CHECK-ALL-LABEL: @cos_f32_massv
364; CHECK-PWR10: __cosf4_P10
365; CHECK-PWR9:  __cosf4_P9
366; CHECK-PWR8:  __cosf4_P8
367; CHECK-PWR7:  __cosf4_P7
368; CHECK-NOT:   __cosf4_massv
369; CHECK-ALL:   blr
370;
371  %1 = call <4 x float> @__cosf4(<4 x float> %opnd)
372  ret <4 x float> %1
373}
374
375; tan
376define <2 x double>  @tan_f64_massv(<2 x double> %opnd) {
377; CHECK-ALL-LABEL: @tan_f64_massv
378; CHECK-PWR10: __tand2_P10
379; CHECK-PWR9:  __tand2_P9
380; CHECK-PWR8:  __tand2_P8
381; CHECK-PWR7:  __tand2_P7
382; CHECK-NOT:   __tand2_massv
383; CHECK-ALL:   blr
384;
385  %1 = call <2 x double> @__tand2(<2 x double> %opnd)
386  ret <2 x double> %1
387}
388
389define <4 x float>  @tan_f32_massv(<4 x float> %opnd) {
390; CHECK-ALL-LABEL: @tan_f32_massv
391; CHECK-PWR10: __tanf4_P10
392; CHECK-PWR9:  __tanf4_P9
393; CHECK-PWR8:  __tanf4_P8
394; CHECK-PWR7:  __tanf4_P7
395; CHECK-NOT:   __tanf4_massv
396; CHECK-ALL:   blr
397;
398  %1 = call <4 x float> @__tanf4(<4 x float> %opnd)
399  ret <4 x float> %1
400}
401
402; asin
403define <2 x double>  @asin_f64_massv(<2 x double> %opnd) {
404; CHECK-ALL-LABEL: @asin_f64_massv
405; CHECK-PWR10: __asind2_P10
406; CHECK-PWR9:  __asind2_P9
407; CHECK-PWR8:  __asind2_P8
408; CHECK-PWR7:  __asind2_P7
409; CHECK-NOT:   __asind2_massv
410; CHECK-ALL:   blr
411;
412  %1 = call <2 x double> @__asind2(<2 x double> %opnd)
413  ret <2 x double> %1
414}
415
416define <4 x float>  @asin_f32_massv(<4 x float> %opnd) {
417; CHECK-ALL-LABEL: @asin_f32_massv
418; CHECK-PWR10: __asinf4_P10
419; CHECK-PWR9:  __asinf4_P9
420; CHECK-PWR8:  __asinf4_P8
421; CHECK-PWR7:  __asinf4_P7
422; CHECK-NOT:   __asinf4_massv
423; CHECK-ALL:   blr
424;
425  %1 = call <4 x float> @__asinf4(<4 x float> %opnd)
426  ret <4 x float> %1
427}
428
429; acos
430define <2 x double>  @acos_f64_massv(<2 x double> %opnd) {
431; CHECK-ALL-LABEL: @acos_f64_massv
432; CHECK-PWR10: __acosd2_P10
433; CHECK-PWR9:  __acosd2_P9
434; CHECK-PWR8:  __acosd2_P8
435; CHECK-PWR7:  __acosd2_P7
436; CHECK-NOT:   __acosd2_massv
437; CHECK-ALL:   blr
438;
439  %1 = call <2 x double> @__acosd2(<2 x double> %opnd)
440  ret <2 x double> %1
441}
442
443define <4 x float>  @acos_f32_massv(<4 x float> %opnd) {
444; CHECK-ALL-LABEL: @acos_f32_massv
445; CHECK-PWR10: __acosf4_P10
446; CHECK-PWR9:  __acosf4_P9
447; CHECK-PWR8:  __acosf4_P8
448; CHECK-PWR7:  __acosf4_P7
449; CHECK-NOT:   __acosf4_massv
450; CHECK-ALL:   blr
451;
452  %1 = call <4 x float> @__acosf4(<4 x float> %opnd)
453  ret <4 x float> %1
454}
455
456; atan
457define <2 x double>  @atan_f64_massv(<2 x double> %opnd) {
458; CHECK-ALL-LABEL: @atan_f64_massv
459; CHECK-PWR10: __atand2_P10
460; CHECK-PWR9:  __atand2_P9
461; CHECK-PWR8:  __atand2_P8
462; CHECK-PWR7:  __atand2_P7
463; CHECK-NOT:   __atand2_massv
464; CHECK-ALL:   blr
465;
466  %1 = call <2 x double> @__atand2(<2 x double> %opnd)
467  ret <2 x double> %1
468}
469
470define <4 x float>  @atan_f32_massv(<4 x float> %opnd) {
471; CHECK-ALL-LABEL: @atan_f32_massv
472; CHECK-PWR10: __atanf4_P10
473; CHECK-PWR9:  __atanf4_P9
474; CHECK-PWR8:  __atanf4_P8
475; CHECK-PWR7:  __atanf4_P7
476; CHECK-NOT:   __atanf4_massv
477; CHECK-ALL:   blr
478;
479  %1 = call <4 x float> @__atanf4(<4 x float> %opnd)
480  ret <4 x float> %1
481}
482
483; atan2
484define <2 x double>  @atan2_f64_massv(<2 x double> %opnd) {
485; CHECK-ALL-LABEL: @atan2_f64_massv
486; CHECK-PWR10: __atan2d2_P10
487; CHECK-PWR9:  __atan2d2_P9
488; CHECK-PWR8:  __atan2d2_P8
489; CHECK-PWR7:  __atan2d2_P7
490; CHECK-NOT:   __atan2d2_massv
491; CHECK-ALL:   blr
492;
493  %1 = call <2 x double> @__atan2d2(<2 x double> %opnd)
494  ret <2 x double> %1
495}
496
497define <4 x float>  @atan2_f32_massv(<4 x float> %opnd) {
498; CHECK-ALL-LABEL: @atan2_f32_massv
499; CHECK-PWR10: __atan2f4_P10
500; CHECK-PWR9:  __atan2f4_P9
501; CHECK-PWR8:  __atan2f4_P8
502; CHECK-PWR7:  __atan2f4_P7
503; CHECK-NOT:   __atan2f4_massv
504; CHECK-ALL:   blr
505;
506  %1 = call <4 x float> @__atan2f4(<4 x float> %opnd)
507  ret <4 x float> %1
508}
509
510; sinh
511define <2 x double>  @sinh_f64_massv(<2 x double> %opnd) {
512; CHECK-ALL-LABEL: @sinh_f64_massv
513; CHECK-PWR10: __sinhd2_P10
514; CHECK-PWR9:  __sinhd2_P9
515; CHECK-PWR8:  __sinhd2_P8
516; CHECK-PWR7:  __sinhd2_P7
517; CHECK-NOT:   __sinhd2_massv
518; CHECK-ALL:   blr
519;
520  %1 = call <2 x double> @__sinhd2(<2 x double> %opnd)
521  ret <2 x double> %1
522}
523
524define <4 x float>  @sinh_f32_massv(<4 x float> %opnd) {
525; CHECK-ALL-LABEL: @sinh_f32_massv
526; CHECK-PWR10: __sinhf4_P10
527; CHECK-PWR9:  __sinhf4_P9
528; CHECK-PWR8:  __sinhf4_P8
529; CHECK-PWR7:  __sinhf4_P7
530; CHECK-NOT:   __sinhf4_massv
531; CHECK-ALL:   blr
532;
533  %1 = call <4 x float> @__sinhf4(<4 x float> %opnd)
534  ret <4 x float> %1
535}
536
537; cosh
538define <2 x double>  @cosh_f64_massv(<2 x double> %opnd) {
539; CHECK-ALL-LABEL: @cosh_f64_massv
540; CHECK-PWR10: __coshd2_P10
541; CHECK-PWR9:  __coshd2_P9
542; CHECK-PWR8:  __coshd2_P8
543; CHECK-PWR7:  __coshd2_P7
544; CHECK-NOT:   __coshd2_massv
545; CHECK-ALL:   blr
546;
547  %1 = call <2 x double> @__coshd2(<2 x double> %opnd)
548  ret <2 x double> %1
549}
550
551define <4 x float>  @cosh_f32_massv(<4 x float> %opnd) {
552; CHECK-ALL-LABEL: @cosh_f32_massv
553; CHECK-PWR10: __coshf4_P10
554; CHECK-PWR9:  __coshf4_P9
555; CHECK-PWR8:  __coshf4_P8
556; CHECK-PWR7:  __coshf4_P7
557; CHECK-NOT:   __coshf4_massv
558; CHECK-ALL:   blr
559;
560  %1 = call <4 x float> @__coshf4(<4 x float> %opnd)
561  ret <4 x float> %1
562}
563
564; tanh
565define <2 x double>  @tanh_f64_massv(<2 x double> %opnd) {
566; CHECK-ALL-LABEL: @tanh_f64_massv
567; CHECK-PWR10: __tanhd2_P10
568; CHECK-PWR9:  __tanhd2_P9
569; CHECK-PWR8:  __tanhd2_P8
570; CHECK-PWR7:  __tanhd2_P7
571; CHECK-NOT:   __tanhd2_massv
572; CHECK-ALL:   blr
573;
574  %1 = call <2 x double> @__tanhd2(<2 x double> %opnd)
575  ret <2 x double> %1
576}
577
578define <4 x float>  @tanh_f32_massv(<4 x float> %opnd) {
579; CHECK-ALL-LABEL: @tanh_f32_massv
580; CHECK-PWR10: __tanhf4_P10
581; CHECK-PWR9:  __tanhf4_P9
582; CHECK-PWR8:  __tanhf4_P8
583; CHECK-PWR7:  __tanhf4_P7
584; CHECK-NOT:   __tanhf4_massv
585; CHECK-ALL:   blr
586;
587  %1 = call <4 x float> @__tanhf4(<4 x float> %opnd)
588  ret <4 x float> %1
589}
590
591; asinh
592define <2 x double>  @asinh_f64_massv(<2 x double> %opnd) {
593; CHECK-ALL-LABEL: @asinh_f64_massv
594; CHECK-PWR10: __asinhd2_P10
595; CHECK-PWR9:  __asinhd2_P9
596; CHECK-PWR8:  __asinhd2_P8
597; CHECK-PWR7:  __asinhd2_P7
598; CHECK-NOT:   __asinhd2_massv
599; CHECK-ALL:   blr
600;
601  %1 = call <2 x double> @__asinhd2(<2 x double> %opnd)
602  ret <2 x double> %1
603}
604
605define <4 x float>  @asinh_f32_massv(<4 x float> %opnd) {
606; CHECK-ALL-LABEL: @asinh_f32_massv
607; CHECK-PWR10: __asinhf4_P10
608; CHECK-PWR9:  __asinhf4_P9
609; CHECK-PWR8:  __asinhf4_P8
610; CHECK-PWR7:  __asinhf4_P7
611; CHECK-NOT:   __asinhf4_massv
612; CHECK-ALL:   blr
613;
614  %1 = call <4 x float> @__asinhf4(<4 x float> %opnd)
615  ret <4 x float> %1
616}
617
618; acosh
619define <2 x double>  @acosh_f64_massv(<2 x double> %opnd) {
620; CHECK-ALL-LABEL: @acosh_f64_massv
621; CHECK-PWR10: __acoshd2_P10
622; CHECK-PWR9:  __acoshd2_P9
623; CHECK-PWR8:  __acoshd2_P8
624; CHECK-PWR7:  __acoshd2_P7
625; CHECK-NOT:   __acoshd2_massv
626; CHECK-ALL:   blr
627;
628  %1 = call <2 x double> @__acoshd2(<2 x double> %opnd)
629  ret <2 x double> %1
630}
631
632define <4 x float>  @acosh_f32_massv(<4 x float> %opnd) {
633; CHECK-ALL-LABEL: @acosh_f32_massv
634; CHECK-PWR10: __acoshf4_P10
635; CHECK-PWR9:  __acoshf4_P9
636; CHECK-PWR8:  __acoshf4_P8
637; CHECK-PWR7:  __acoshf4_P7
638; CHECK-NOT:   __acoshf4_massv
639; CHECK-ALL:   blr
640;
641  %1 = call <4 x float> @__acoshf4(<4 x float> %opnd)
642  ret <4 x float> %1
643}
644
645; atanh
646define <2 x double>  @atanh_f64_massv(<2 x double> %opnd) {
647; CHECK-ALL-LABEL: @atanh_f64_massv
648; CHECK-PWR10: __atanhd2_P10
649; CHECK-PWR9:  __atanhd2_P9
650; CHECK-PWR8:  __atanhd2_P8
651; CHECK-PWR7:  __atanhd2_P7
652; CHECK-NOT:   __atanhd2_massv
653; CHECK-ALL:   blr
654;
655  %1 = call <2 x double> @__atanhd2(<2 x double> %opnd)
656  ret <2 x double> %1
657}
658
659define <4 x float>  @atanh_f32_massv(<4 x float> %opnd) {
660; CHECK-ALL-LABEL: @atanh_f32_massv
661; CHECK-PWR10: __atanhf4_P10
662; CHECK-PWR9:  __atanhf4_P9
663; CHECK-PWR8:  __atanhf4_P8
664; CHECK-PWR7:  __atanhf4_P7
665; CHECK-NOT:   __atanhf4_massv
666; CHECK-ALL:   blr
667;
668  %1 = call <4 x float> @__atanhf4(<4 x float> %opnd)
669  ret <4 x float> %1
670}
671
672