1; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s 2; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s 3 4declare float @llvm.cos.f32(float) 5declare float @llvm.exp.f32(float) 6declare float @llvm.log10.f32(float) 7declare float @llvm.log.f32(float) 8declare float @llvm.pow.f32(float, float) 9declare float @llvm.rint.f32(float) 10declare float @llvm.sin.f32(float) 11declare double @llvm.cos.f64(double) 12declare double @llvm.exp.f64(double) 13declare double @llvm.log.f64(double) 14declare double @llvm.log10.f64(double) 15declare double @llvm.pow.f64(double, double) 16declare double @llvm.sin.f64(double) 17 18; With afn flag specified per-function 19define float @cosf_f32(float %a) { 20; CHECK-LABEL: cosf_f32 21; CHECK: __xl_cosf 22; CHECK: blr 23entry: 24 %0 = tail call afn float @llvm.cos.f32(float %a) 25 ret float %0 26} 27 28; With afn flag specified per-function 29define float @expf_f32(float %a) { 30; CHECK-LABEL: expf_f32 31; CHECK: __xl_expf 32; CHECK: blr 33entry: 34 %0 = tail call afn float @llvm.exp.f32(float %a) 35 ret float %0 36} 37 38; With afn flag specified per-function 39define float @log10f_f32(float %a) { 40; CHECK-LABEL: log10f_f32 41; CHECK: __xl_log10f 42; CHECK: blr 43entry: 44 %0 = tail call afn float @llvm.log10.f32(float %a) 45 ret float %0 46} 47 48; With afn flag specified per-function 49define float @logf_f32(float %a) { 50; CHECK-LABEL: logf_f32 51; CHECK: __xl_logf 52; CHECK: blr 53entry: 54 %0 = tail call afn float @llvm.log.f32(float %a) 55 ret float %0 56} 57 58; With afn flag specified per-function 59define float @powf_f32(float %a, float %b) { 60; CHECK-LABEL: powf_f32 61; CHECK: __xl_powf 62; CHECK: blr 63entry: 64 %0 = tail call afn float @llvm.pow.f32(float %a, float %b) 65 ret float %0 66} 67 68; With afn flag specified per-function 69define float @rintf_f32(float %a) { 70; CHECK-LABEL: rintf_f32 71; CHECK-NOT: bl __xl_rintf 72; CHECK: blr 73entry: 74 %0 = tail call afn float @llvm.rint.f32(float %a) 75 ret float %0 76} 77 78; With afn flag specified per-function 79define float @sinf_f32(float %a) { 80; CHECK-LABEL: sinf_f32 81; CHECK: __xl_sinf 82; CHECK: blr 83entry: 84 %0 = tail call afn float @llvm.sin.f32(float %a) 85 ret float %0 86} 87 88; With afn flag specified per-function 89define double @cos_f64(double %a) { 90; CHECK-LABEL: cos_f64 91; CHECK: __xl_cos 92; CHECK: blr 93entry: 94 %0 = tail call afn double @llvm.cos.f64(double %a) 95 ret double %0 96} 97 98; With afn flag specified per-function 99define double @exp_f64(double %a) { 100; CHECK-LABEL: exp_f64 101; CHECK: __xl_exp 102; CHECK: blr 103entry: 104 %0 = tail call afn double @llvm.exp.f64(double %a) 105 ret double %0 106} 107 108; With afn flag specified per-function 109define double @log_f64(double %a) { 110; CHECK-LABEL: log_f64 111; CHECK: __xl_log 112; CHECK: blr 113entry: 114 %0 = tail call afn double @llvm.log.f64(double %a) 115 ret double %0 116} 117 118; With afn flag specified per-function 119define double @log10_f64(double %a) { 120; CHECK-LABEL: log10_f64 121; CHECK: __xl_log10 122; CHECK: blr 123entry: 124 %0 = tail call afn double @llvm.log10.f64(double %a) 125 ret double %0 126} 127 128; With afn flag specified per-function 129define double @pow_f64(double %a, double %b) { 130; CHECK-LABEL: pow_f64 131; CHECK: __xl_pow 132; CHECK: blr 133entry: 134 %0 = tail call afn double @llvm.pow.f64(double %a, double %b) 135 ret double %0 136} 137 138; With afn flag specified per-function 139define double @sin_f64(double %a) { 140; CHECK-LABEL: sin_f64 141; CHECK: __xl_sin 142; CHECK: blr 143entry: 144 %0 = tail call afn double @llvm.sin.f64(double %a) 145 ret double %0 146} 147