1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ 4; RUN: < %s | FileCheck %s --check-prefix=CHECK-P10LE 5 6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 7; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ 8; RUN: < %s | FileCheck %s --check-prefix=CHECK-P10BE 9 10; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 11; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ 12; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 13 14; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 15; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ 16; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 17 18define <8 x i16> @test1(ptr %a) { 19; CHECK-P10LE-LABEL: test1: 20; CHECK-P10LE: # %bb.0: # %entry 21; CHECK-P10LE-NEXT: lxvrhx v2, 0, r3 22; CHECK-P10LE-NEXT: blr 23; 24; CHECK-P10BE-LABEL: test1: 25; CHECK-P10BE: # %bb.0: # %entry 26; CHECK-P10BE-NEXT: lxsihzx v2, 0, r3 27; CHECK-P10BE-NEXT: vsplth v2, v2, 3 28; CHECK-P10BE-NEXT: blr 29; 30; CHECK-P9-LABEL: test1: 31; CHECK-P9: # %bb.0: # %entry 32; CHECK-P9-NEXT: lxsihzx v2, 0, r3 33; CHECK-P9-NEXT: vsplth v2, v2, 3 34; CHECK-P9-NEXT: blr 35entry: 36 %0 = load i16, ptr %a, align 2 37 %vecinit = insertelement <8 x i16> undef, i16 %0, i32 0 38 ret <8 x i16> %vecinit 39} 40 41define <16 x i8> @test2(ptr %a) { 42; CHECK-P10LE-LABEL: test2: 43; CHECK-P10LE: # %bb.0: # %entry 44; CHECK-P10LE-NEXT: lxvrbx v2, 0, r3 45; CHECK-P10LE-NEXT: blr 46; 47; CHECK-P10BE-LABEL: test2: 48; CHECK-P10BE: # %bb.0: # %entry 49; CHECK-P10BE-NEXT: lxsibzx v2, 0, r3 50; CHECK-P10BE-NEXT: vspltb v2, v2, 7 51; CHECK-P10BE-NEXT: blr 52; 53; CHECK-P9-LABEL: test2: 54; CHECK-P9: # %bb.0: # %entry 55; CHECK-P9-NEXT: lxsibzx v2, 0, r3 56; CHECK-P9-NEXT: vspltb v2, v2, 7 57; CHECK-P9-NEXT: blr 58entry: 59 %0 = load i8, ptr %a, align 1 60 %vecins = insertelement <16 x i8> undef, i8 %0, i32 0 61 ret <16 x i8> %vecins 62} 63 64