1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr7 -verify-machineinstrs \ 3; RUN: -mtriple=powerpc-unknown-aix < %s | FileCheck %s --check-prefix=IAS32 4 5; RUN: llc -mcpu=pwr7 -verify-machineinstrs \ 6; RUN: -mtriple=powerpc64-unknown-aix < %s | FileCheck %s --check-prefix=IAS64 7 8; RUN: llc -mcpu=pwr7 -verify-machineinstrs -no-integrated-as \ 9; RUN: -mtriple=powerpc64-unknown-aix < %s | FileCheck %s --check-prefix=NOIAS 10 11define dso_local i32 @dollarpc() #0 { 12; IAS32-LABEL: dollarpc: 13; IAS32: # %bb.0: # %entry 14; IAS32-NEXT: li 3, 0 15; IAS32-NEXT: stw 3, -4(1) 16; IAS32-NEXT: #APP 17; IAS32-NEXT: mfspr 5, 269 18; IAS32-NEXT: mfspr 3, 268 19; IAS32-NEXT: mfspr 4, 269 20; IAS32-NEXT: cmpw 5, 4 21; IAS32-NEXT: L..tmp0: 22; IAS32-NEXT: bne 0, L..tmp0-16 23; IAS32-EMPTY: 24; IAS32-NEXT: #NO_APP 25; IAS32-NEXT: stw 3, -12(1) 26; IAS32-NEXT: stw 4, -8(1) 27; IAS32-NEXT: stw 5, -16(1) 28; IAS32-NEXT: blr 29; 30; IAS64-LABEL: dollarpc: 31; IAS64: # %bb.0: # %entry 32; IAS64-NEXT: li 3, 0 33; IAS64-NEXT: stw 3, -4(1) 34; IAS64-NEXT: #APP 35; IAS64-NEXT: mfspr 4, 269 36; IAS64-NEXT: mfspr 3, 268 37; IAS64-NEXT: mfspr 5, 269 38; IAS64-NEXT: cmpw 4, 5 39; IAS64-NEXT: L..tmp0: 40; IAS64-NEXT: bne 0, L..tmp0-16 41; IAS64-EMPTY: 42; IAS64-NEXT: #NO_APP 43; IAS64-NEXT: stw 3, -12(1) 44; IAS64-NEXT: rldimi 3, 5, 32, 0 45; IAS64-NEXT: stw 5, -8(1) 46; IAS64-NEXT: stw 4, -16(1) 47; IAS64-NEXT: blr 48; 49; NOIAS-LABEL: dollarpc: 50; NOIAS: # %bb.0: # %entry 51; NOIAS-NEXT: li 3, 0 52; NOIAS-NEXT: stw 3, -4(1) 53; NOIAS-NEXT: #APP 54; NOIAS-NEXT: mftbu 4 55; NOIAS-NEXT: mftb 3 56; NOIAS-NEXT: mftbu 5 57; NOIAS-NEXT: cmpw 4,5 58; NOIAS-NEXT: bne $-0x10 59; NOIAS-EMPTY: 60; NOIAS-NEXT: #NO_APP 61; NOIAS-NEXT: stw 3, -12(1) 62; NOIAS-NEXT: rldimi 3, 5, 32, 0 63; NOIAS-NEXT: stw 5, -8(1) 64; NOIAS-NEXT: stw 4, -16(1) 65; NOIAS-NEXT: blr 66entry: 67 %retval = alloca i32, align 4 68 %tbu = alloca i32, align 4 69 %tbl = alloca i32, align 4 70 %temp = alloca i32, align 4 71 store i32 0, ptr %retval, align 4 72 %0 = call { i32, i32, i32 } asm sideeffect "mftbu $2\0Amftb $0\0Amftbu $1\0Acmpw $2,$1\0Abne $$-0x10\0A", "=r,=r,=r,~{cc}"() 73 %asmresult = extractvalue { i32, i32, i32 } %0, 0 74 %asmresult1 = extractvalue { i32, i32, i32 } %0, 1 75 %asmresult2 = extractvalue { i32, i32, i32 } %0, 2 76 store i32 %asmresult, ptr %tbl, align 4 77 store i32 %asmresult1, ptr %tbu, align 4 78 store i32 %asmresult2, ptr %temp, align 4 79 %1 = load i32, ptr %tbu, align 4 80 %conv = zext i32 %1 to i64 81 %shl = shl i64 %conv, 32 82 %2 = load i32, ptr %tbl, align 4 83 %conv3 = zext i32 %2 to i64 84 %or = or i64 %shl, %conv3 85 %conv4 = trunc i64 %or to i32 86 ret i32 %conv4 87} 88 89