xref: /llvm-project/llvm/test/CodeGen/PowerPC/frameaddr-alloca.ll (revision e1c03ddc9b03b820b421d8b3bca6a94e4d1a4675)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -mcpu=pwr7 | FileCheck %s --check-prefix=AIX32
3; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s -mcpu=pwr7 | FileCheck %s --check-prefix=AIX64
4; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s -mcpu=pwr7 | FileCheck %s --check-prefix=LE
5
6define ptr @frame_1(i32 signext %num) nounwind {
7; AIX32-LABEL: frame_1:
8; AIX32:       # %bb.0: # %entry
9; AIX32-NEXT:    stw 31, -4(1)
10; AIX32-NEXT:    stwu 1, -48(1)
11; AIX32-NEXT:    addi 3, 3, 15
12; AIX32-NEXT:    mr 31, 1
13; AIX32-NEXT:    addi 4, 31, 48
14; AIX32-NEXT:    rlwinm 3, 3, 0, 0, 27
15; AIX32-NEXT:    neg 3, 3
16; AIX32-NEXT:    stwux 4, 1, 3
17; AIX32-NEXT:    addi 3, 1, 32
18; AIX32-NEXT:    lbz 4, 0(3)
19; AIX32-NEXT:    addi 4, 4, 1
20; AIX32-NEXT:    stb 4, 0(3)
21; AIX32-NEXT:    lwz 3, 0(1)
22; AIX32-NEXT:    lwz 1, 0(1)
23; AIX32-NEXT:    lwz 31, -4(1)
24; AIX32-NEXT:    blr
25;
26; AIX64-LABEL: frame_1:
27; AIX64:       # %bb.0: # %entry
28; AIX64-NEXT:    std 31, -8(1)
29; AIX64-NEXT:    stdu 1, -64(1)
30; AIX64-NEXT:    addi 3, 3, 15
31; AIX64-NEXT:    mr 31, 1
32; AIX64-NEXT:    addi 4, 31, 64
33; AIX64-NEXT:    rldicr 3, 3, 0, 59
34; AIX64-NEXT:    neg 3, 3
35; AIX64-NEXT:    stdux 4, 1, 3
36; AIX64-NEXT:    addi 3, 1, 48
37; AIX64-NEXT:    lbz 4, 0(3)
38; AIX64-NEXT:    addi 4, 4, 1
39; AIX64-NEXT:    stb 4, 0(3)
40; AIX64-NEXT:    ld 3, 0(1)
41; AIX64-NEXT:    ld 1, 0(1)
42; AIX64-NEXT:    ld 31, -8(1)
43; AIX64-NEXT:    blr
44;
45; LE-LABEL: frame_1:
46; LE:       # %bb.0: # %entry
47; LE-NEXT:    std 31, -8(1)
48; LE-NEXT:    stdu 1, -48(1)
49; LE-NEXT:    addi 3, 3, 15
50; LE-NEXT:    mr 31, 1
51; LE-NEXT:    addi 4, 31, 48
52; LE-NEXT:    rldicr 3, 3, 0, 59
53; LE-NEXT:    neg 3, 3
54; LE-NEXT:    stdux 4, 1, 3
55; LE-NEXT:    addi 3, 1, 32
56; LE-NEXT:    lbz 4, 0(3)
57; LE-NEXT:    addi 4, 4, 1
58; LE-NEXT:    stb 4, 0(3)
59; LE-NEXT:    ld 3, 0(1)
60; LE-NEXT:    ld 1, 0(1)
61; LE-NEXT:    ld 31, -8(1)
62; LE-NEXT:    blr
63entry:
64  %conv = sext i32 %num to i64
65  %0 = alloca i8, i64 %conv, align 16
66  %1 = load volatile i8, ptr %0, align 16
67  %inc = add i8 %1, 1
68  store volatile i8 %inc, ptr %0, align 16
69  %2 = tail call ptr @llvm.frameaddress.p0(i32 1)
70  ret ptr %2
71}
72
73define ptr @frame_0(i32 signext %num) nounwind {
74; AIX32-LABEL: frame_0:
75; AIX32:       # %bb.0: # %entry
76; AIX32-NEXT:    stw 31, -4(1)
77; AIX32-NEXT:    stwu 1, -48(1)
78; AIX32-NEXT:    addi 3, 3, 15
79; AIX32-NEXT:    mr 31, 1
80; AIX32-NEXT:    addi 4, 31, 48
81; AIX32-NEXT:    rlwinm 3, 3, 0, 0, 27
82; AIX32-NEXT:    neg 3, 3
83; AIX32-NEXT:    stwux 4, 1, 3
84; AIX32-NEXT:    addi 3, 1, 32
85; AIX32-NEXT:    lbz 4, 0(3)
86; AIX32-NEXT:    addi 4, 4, 1
87; AIX32-NEXT:    stb 4, 0(3)
88; AIX32-NEXT:    mr 3, 1
89; AIX32-NEXT:    lwz 1, 0(1)
90; AIX32-NEXT:    lwz 31, -4(1)
91; AIX32-NEXT:    blr
92;
93; AIX64-LABEL: frame_0:
94; AIX64:       # %bb.0: # %entry
95; AIX64-NEXT:    std 31, -8(1)
96; AIX64-NEXT:    stdu 1, -64(1)
97; AIX64-NEXT:    addi 3, 3, 15
98; AIX64-NEXT:    mr 31, 1
99; AIX64-NEXT:    addi 4, 31, 64
100; AIX64-NEXT:    rldicr 3, 3, 0, 59
101; AIX64-NEXT:    neg 3, 3
102; AIX64-NEXT:    stdux 4, 1, 3
103; AIX64-NEXT:    addi 3, 1, 48
104; AIX64-NEXT:    lbz 4, 0(3)
105; AIX64-NEXT:    addi 4, 4, 1
106; AIX64-NEXT:    stb 4, 0(3)
107; AIX64-NEXT:    mr 3, 1
108; AIX64-NEXT:    ld 1, 0(1)
109; AIX64-NEXT:    ld 31, -8(1)
110; AIX64-NEXT:    blr
111;
112; LE-LABEL: frame_0:
113; LE:       # %bb.0: # %entry
114; LE-NEXT:    std 31, -8(1)
115; LE-NEXT:    stdu 1, -48(1)
116; LE-NEXT:    addi 3, 3, 15
117; LE-NEXT:    mr 31, 1
118; LE-NEXT:    addi 4, 31, 48
119; LE-NEXT:    rldicr 3, 3, 0, 59
120; LE-NEXT:    neg 3, 3
121; LE-NEXT:    stdux 4, 1, 3
122; LE-NEXT:    addi 3, 1, 32
123; LE-NEXT:    lbz 4, 0(3)
124; LE-NEXT:    addi 4, 4, 1
125; LE-NEXT:    stb 4, 0(3)
126; LE-NEXT:    mr 3, 1
127; LE-NEXT:    ld 1, 0(1)
128; LE-NEXT:    ld 31, -8(1)
129; LE-NEXT:    blr
130entry:
131  %conv = sext i32 %num to i64
132  %0 = alloca i8, i64 %conv, align 16
133  %1 = load volatile i8, ptr %0, align 16
134  %inc = add i8 %1, 1
135  store volatile i8 %inc, ptr %0, align 16
136  %2 = tail call ptr @llvm.frameaddress.p0(i32 0)
137  ret ptr %2
138}
139