1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc-unknown-linux -mattr=spe | FileCheck %s -check-prefix=SPE 3 4define i32 @test_f32_oeq_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 5; SPE-LABEL: test_f32_oeq_s: 6; SPE: # %bb.0: 7; SPE-NEXT: efscmpeq cr0, r5, r6 8; SPE-NEXT: bclr 12, gt, 0 9; SPE-NEXT: # %bb.1: 10; SPE-NEXT: mr r3, r4 11; SPE-NEXT: blr 12 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"oeq", metadata !"fpexcept.strict") #0 13 %res = select i1 %cond, i32 %a, i32 %b 14 ret i32 %res 15} 16 17define i32 @test_f32_ogt_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 18; SPE-LABEL: test_f32_ogt_s: 19; SPE: # %bb.0: 20; SPE-NEXT: efscmpgt cr0, r5, r6 21; SPE-NEXT: bclr 12, gt, 0 22; SPE-NEXT: # %bb.1: 23; SPE-NEXT: mr r3, r4 24; SPE-NEXT: blr 25 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ogt", metadata !"fpexcept.strict") #0 26 %res = select i1 %cond, i32 %a, i32 %b 27 ret i32 %res 28} 29 30define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 31; SPE-LABEL: test_f32_oge_s: 32; SPE: # %bb.0: 33; SPE-NEXT: efscmpeq cr0, r6, r6 34; SPE-NEXT: bc 4, gt, .LBB2_3 35; SPE-NEXT: # %bb.1: 36; SPE-NEXT: efscmpeq cr0, r5, r5 37; SPE-NEXT: bc 4, gt, .LBB2_3 38; SPE-NEXT: # %bb.2: 39; SPE-NEXT: efscmplt cr0, r5, r6 40; SPE-NEXT: bclr 4, gt, 0 41; SPE-NEXT: .LBB2_3: 42; SPE-NEXT: mr r3, r4 43; SPE-NEXT: blr 44 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"oge", metadata !"fpexcept.strict") #0 45 %res = select i1 %cond, i32 %a, i32 %b 46 ret i32 %res 47} 48 49define i32 @test_f32_olt_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 50; SPE-LABEL: test_f32_olt_s: 51; SPE: # %bb.0: 52; SPE-NEXT: efscmplt cr0, r5, r6 53; SPE-NEXT: bclr 12, gt, 0 54; SPE-NEXT: # %bb.1: 55; SPE-NEXT: mr r3, r4 56; SPE-NEXT: blr 57 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"olt", metadata !"fpexcept.strict") #0 58 %res = select i1 %cond, i32 %a, i32 %b 59 ret i32 %res 60} 61 62define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 63; SPE-LABEL: test_f32_ole_s: 64; SPE: # %bb.0: 65; SPE-NEXT: efscmpeq cr0, r6, r6 66; SPE-NEXT: bc 4, gt, .LBB4_3 67; SPE-NEXT: # %bb.1: 68; SPE-NEXT: efscmpeq cr0, r5, r5 69; SPE-NEXT: bc 4, gt, .LBB4_3 70; SPE-NEXT: # %bb.2: 71; SPE-NEXT: efscmpgt cr0, r5, r6 72; SPE-NEXT: bclr 4, gt, 0 73; SPE-NEXT: .LBB4_3: 74; SPE-NEXT: mr r3, r4 75; SPE-NEXT: blr 76 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ole", metadata !"fpexcept.strict") #0 77 %res = select i1 %cond, i32 %a, i32 %b 78 ret i32 %res 79} 80 81define i32 @test_f32_one_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 82; SPE-LABEL: test_f32_one_s: 83; SPE: # %bb.0: 84; SPE-NEXT: efscmplt cr0, r5, r6 85; SPE-NEXT: bclr 12, gt, 0 86; SPE-NEXT: # %bb.1: 87; SPE-NEXT: efscmpgt cr0, r5, r6 88; SPE-NEXT: bclr 12, gt, 0 89; SPE-NEXT: # %bb.2: 90; SPE-NEXT: mr r3, r4 91; SPE-NEXT: blr 92 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"one", metadata !"fpexcept.strict") #0 93 %res = select i1 %cond, i32 %a, i32 %b 94 ret i32 %res 95} 96 97define i32 @test_f32_ord_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 98; SPE-LABEL: test_f32_ord_s: 99; SPE: # %bb.0: 100; SPE-NEXT: efscmpeq cr0, r6, r6 101; SPE-NEXT: bc 4, gt, .LBB6_2 102; SPE-NEXT: # %bb.1: 103; SPE-NEXT: efscmpeq cr0, r5, r5 104; SPE-NEXT: bclr 12, gt, 0 105; SPE-NEXT: .LBB6_2: 106; SPE-NEXT: mr r3, r4 107; SPE-NEXT: blr 108 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ord", metadata !"fpexcept.strict") #0 109 %res = select i1 %cond, i32 %a, i32 %b 110 ret i32 %res 111} 112 113define i32 @test_f32_ueq_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 114; SPE-LABEL: test_f32_ueq_s: 115; SPE: # %bb.0: 116; SPE-NEXT: efscmplt cr0, r5, r6 117; SPE-NEXT: bc 12, gt, .LBB7_3 118; SPE-NEXT: # %bb.1: 119; SPE-NEXT: efscmpgt cr0, r5, r6 120; SPE-NEXT: bc 12, gt, .LBB7_3 121; SPE-NEXT: # %bb.2: 122; SPE-NEXT: mr r4, r3 123; SPE-NEXT: .LBB7_3: 124; SPE-NEXT: mr r3, r4 125; SPE-NEXT: blr 126 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ueq", metadata !"fpexcept.strict") #0 127 %res = select i1 %cond, i32 %a, i32 %b 128 ret i32 %res 129} 130 131define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 132; SPE-LABEL: test_f32_ugt_s: 133; SPE: # %bb.0: 134; SPE-NEXT: efscmpeq cr0, r5, r5 135; SPE-NEXT: bclr 4, gt, 0 136; SPE-NEXT: # %bb.1: 137; SPE-NEXT: efscmpeq cr0, r6, r6 138; SPE-NEXT: bclr 4, gt, 0 139; SPE-NEXT: # %bb.2: 140; SPE-NEXT: efscmpgt cr0, r5, r6 141; SPE-NEXT: bclr 12, gt, 0 142; SPE-NEXT: # %bb.3: 143; SPE-NEXT: mr r3, r4 144; SPE-NEXT: blr 145 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ugt", metadata !"fpexcept.strict") #0 146 %res = select i1 %cond, i32 %a, i32 %b 147 ret i32 %res 148} 149 150define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 151; SPE-LABEL: test_f32_uge_s: 152; SPE: # %bb.0: 153; SPE-NEXT: efscmplt cr0, r5, r6 154; SPE-NEXT: bc 12, gt, .LBB9_2 155; SPE-NEXT: # %bb.1: 156; SPE-NEXT: mr r4, r3 157; SPE-NEXT: .LBB9_2: 158; SPE-NEXT: mr r3, r4 159; SPE-NEXT: blr 160 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"uge", metadata !"fpexcept.strict") #0 161 %res = select i1 %cond, i32 %a, i32 %b 162 ret i32 %res 163} 164 165define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 166; SPE-LABEL: test_f32_ult_s: 167; SPE: # %bb.0: 168; SPE-NEXT: efscmpeq cr0, r5, r5 169; SPE-NEXT: bclr 4, gt, 0 170; SPE-NEXT: # %bb.1: 171; SPE-NEXT: efscmpeq cr0, r6, r6 172; SPE-NEXT: bclr 4, gt, 0 173; SPE-NEXT: # %bb.2: 174; SPE-NEXT: efscmplt cr0, r5, r6 175; SPE-NEXT: bclr 12, gt, 0 176; SPE-NEXT: # %bb.3: 177; SPE-NEXT: mr r3, r4 178; SPE-NEXT: blr 179 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ult", metadata !"fpexcept.strict") #0 180 %res = select i1 %cond, i32 %a, i32 %b 181 ret i32 %res 182} 183 184define i32 @test_f32_ule_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 185; SPE-LABEL: test_f32_ule_s: 186; SPE: # %bb.0: 187; SPE-NEXT: efscmpgt cr0, r5, r6 188; SPE-NEXT: bc 12, gt, .LBB11_2 189; SPE-NEXT: # %bb.1: 190; SPE-NEXT: mr r4, r3 191; SPE-NEXT: .LBB11_2: 192; SPE-NEXT: mr r3, r4 193; SPE-NEXT: blr 194 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ule", metadata !"fpexcept.strict") #0 195 %res = select i1 %cond, i32 %a, i32 %b 196 ret i32 %res 197} 198 199define i32 @test_f32_une_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 200; SPE-LABEL: test_f32_une_s: 201; SPE: # %bb.0: 202; SPE-NEXT: efscmpeq cr0, r5, r6 203; SPE-NEXT: bc 12, gt, .LBB12_2 204; SPE-NEXT: # %bb.1: 205; SPE-NEXT: mr r4, r3 206; SPE-NEXT: .LBB12_2: 207; SPE-NEXT: mr r3, r4 208; SPE-NEXT: blr 209 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"une", metadata !"fpexcept.strict") #0 210 %res = select i1 %cond, i32 %a, i32 %b 211 ret i32 %res 212} 213 214define i32 @test_f32_uno_s(i32 %a, i32 %b, float %f1, float %f2) #0 { 215; SPE-LABEL: test_f32_uno_s: 216; SPE: # %bb.0: 217; SPE-NEXT: efscmpeq cr0, r5, r5 218; SPE-NEXT: bclr 4, gt, 0 219; SPE-NEXT: # %bb.1: 220; SPE-NEXT: efscmpeq cr0, r6, r6 221; SPE-NEXT: bclr 4, gt, 0 222; SPE-NEXT: # %bb.2: 223; SPE-NEXT: mr r3, r4 224; SPE-NEXT: blr 225 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"uno", metadata !"fpexcept.strict") #0 226 %res = select i1 %cond, i32 %a, i32 %b 227 ret i32 %res 228} 229 230define i32 @test_f64_oeq_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 231; SPE-LABEL: test_f64_oeq_s: 232; SPE: # %bb.0: 233; SPE-NEXT: evmergelo r7, r7, r8 234; SPE-NEXT: evmergelo r5, r5, r6 235; SPE-NEXT: efdcmpeq cr0, r5, r7 236; SPE-NEXT: bclr 12, gt, 0 237; SPE-NEXT: # %bb.1: 238; SPE-NEXT: mr r3, r4 239; SPE-NEXT: blr 240 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"oeq", metadata !"fpexcept.strict") #0 241 %res = select i1 %cond, i32 %a, i32 %b 242 ret i32 %res 243} 244 245define i32 @test_f64_ogt_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 246; SPE-LABEL: test_f64_ogt_s: 247; SPE: # %bb.0: 248; SPE-NEXT: evmergelo r7, r7, r8 249; SPE-NEXT: evmergelo r5, r5, r6 250; SPE-NEXT: efdcmpgt cr0, r5, r7 251; SPE-NEXT: bclr 12, gt, 0 252; SPE-NEXT: # %bb.1: 253; SPE-NEXT: mr r3, r4 254; SPE-NEXT: blr 255 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ogt", metadata !"fpexcept.strict") #0 256 %res = select i1 %cond, i32 %a, i32 %b 257 ret i32 %res 258} 259 260define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 261; SPE-LABEL: test_f64_oge_s: 262; SPE: # %bb.0: 263; SPE-NEXT: evmergelo r5, r5, r6 264; SPE-NEXT: evmergelo r6, r7, r8 265; SPE-NEXT: efdcmpeq cr0, r6, r6 266; SPE-NEXT: bc 4, gt, .LBB16_3 267; SPE-NEXT: # %bb.1: 268; SPE-NEXT: efdcmpeq cr0, r5, r5 269; SPE-NEXT: bc 4, gt, .LBB16_3 270; SPE-NEXT: # %bb.2: 271; SPE-NEXT: efdcmplt cr0, r5, r6 272; SPE-NEXT: bclr 4, gt, 0 273; SPE-NEXT: .LBB16_3: 274; SPE-NEXT: mr r3, r4 275; SPE-NEXT: blr 276 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"oge", metadata !"fpexcept.strict") #0 277 %res = select i1 %cond, i32 %a, i32 %b 278 ret i32 %res 279} 280 281define i32 @test_f64_olt_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 282; SPE-LABEL: test_f64_olt_s: 283; SPE: # %bb.0: 284; SPE-NEXT: evmergelo r7, r7, r8 285; SPE-NEXT: evmergelo r5, r5, r6 286; SPE-NEXT: efdcmplt cr0, r5, r7 287; SPE-NEXT: bclr 12, gt, 0 288; SPE-NEXT: # %bb.1: 289; SPE-NEXT: mr r3, r4 290; SPE-NEXT: blr 291 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"olt", metadata !"fpexcept.strict") #0 292 %res = select i1 %cond, i32 %a, i32 %b 293 ret i32 %res 294} 295 296define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 297; SPE-LABEL: test_f64_ole_s: 298; SPE: # %bb.0: 299; SPE-NEXT: evmergelo r5, r5, r6 300; SPE-NEXT: evmergelo r6, r7, r8 301; SPE-NEXT: efdcmpeq cr0, r6, r6 302; SPE-NEXT: bc 4, gt, .LBB18_3 303; SPE-NEXT: # %bb.1: 304; SPE-NEXT: efdcmpeq cr0, r5, r5 305; SPE-NEXT: bc 4, gt, .LBB18_3 306; SPE-NEXT: # %bb.2: 307; SPE-NEXT: efdcmpgt cr0, r5, r6 308; SPE-NEXT: bclr 4, gt, 0 309; SPE-NEXT: .LBB18_3: 310; SPE-NEXT: mr r3, r4 311; SPE-NEXT: blr 312 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ole", metadata !"fpexcept.strict") #0 313 %res = select i1 %cond, i32 %a, i32 %b 314 ret i32 %res 315} 316 317define i32 @test_f64_one_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 318; SPE-LABEL: test_f64_one_s: 319; SPE: # %bb.0: 320; SPE-NEXT: evmergelo r7, r7, r8 321; SPE-NEXT: evmergelo r5, r5, r6 322; SPE-NEXT: efdcmplt cr0, r5, r7 323; SPE-NEXT: bclr 12, gt, 0 324; SPE-NEXT: # %bb.1: 325; SPE-NEXT: efdcmpgt cr0, r5, r7 326; SPE-NEXT: bclr 12, gt, 0 327; SPE-NEXT: # %bb.2: 328; SPE-NEXT: mr r3, r4 329; SPE-NEXT: blr 330 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"one", metadata !"fpexcept.strict") #0 331 %res = select i1 %cond, i32 %a, i32 %b 332 ret i32 %res 333} 334 335define i32 @test_f64_ord_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 336; SPE-LABEL: test_f64_ord_s: 337; SPE: # %bb.0: 338; SPE-NEXT: evmergelo r5, r5, r6 339; SPE-NEXT: evmergelo r6, r7, r8 340; SPE-NEXT: efdcmpeq cr0, r6, r6 341; SPE-NEXT: bc 4, gt, .LBB20_2 342; SPE-NEXT: # %bb.1: 343; SPE-NEXT: efdcmpeq cr0, r5, r5 344; SPE-NEXT: bclr 12, gt, 0 345; SPE-NEXT: .LBB20_2: 346; SPE-NEXT: mr r3, r4 347; SPE-NEXT: blr 348 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ord", metadata !"fpexcept.strict") #0 349 %res = select i1 %cond, i32 %a, i32 %b 350 ret i32 %res 351} 352 353define i32 @test_f64_ueq_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 354; SPE-LABEL: test_f64_ueq_s: 355; SPE: # %bb.0: 356; SPE-NEXT: evmergelo r7, r7, r8 357; SPE-NEXT: evmergelo r5, r5, r6 358; SPE-NEXT: efdcmplt cr0, r5, r7 359; SPE-NEXT: bc 12, gt, .LBB21_3 360; SPE-NEXT: # %bb.1: 361; SPE-NEXT: efdcmpgt cr0, r5, r7 362; SPE-NEXT: bc 12, gt, .LBB21_3 363; SPE-NEXT: # %bb.2: 364; SPE-NEXT: mr r4, r3 365; SPE-NEXT: .LBB21_3: 366; SPE-NEXT: mr r3, r4 367; SPE-NEXT: blr 368 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ueq", metadata !"fpexcept.strict") #0 369 %res = select i1 %cond, i32 %a, i32 %b 370 ret i32 %res 371} 372 373define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 374; SPE-LABEL: test_f64_ugt_s: 375; SPE: # %bb.0: 376; SPE-NEXT: evmergelo r7, r7, r8 377; SPE-NEXT: evmergelo r5, r5, r6 378; SPE-NEXT: efdcmpeq cr0, r5, r5 379; SPE-NEXT: bclr 4, gt, 0 380; SPE-NEXT: # %bb.1: 381; SPE-NEXT: efdcmpeq cr0, r7, r7 382; SPE-NEXT: bclr 4, gt, 0 383; SPE-NEXT: # %bb.2: 384; SPE-NEXT: efdcmpgt cr0, r5, r7 385; SPE-NEXT: bclr 12, gt, 0 386; SPE-NEXT: # %bb.3: 387; SPE-NEXT: mr r3, r4 388; SPE-NEXT: blr 389 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ugt", metadata !"fpexcept.strict") #0 390 %res = select i1 %cond, i32 %a, i32 %b 391 ret i32 %res 392} 393 394define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 395; SPE-LABEL: test_f64_uge_s: 396; SPE: # %bb.0: 397; SPE-NEXT: evmergelo r7, r7, r8 398; SPE-NEXT: evmergelo r5, r5, r6 399; SPE-NEXT: efdcmplt cr0, r5, r7 400; SPE-NEXT: bc 12, gt, .LBB23_2 401; SPE-NEXT: # %bb.1: 402; SPE-NEXT: mr r4, r3 403; SPE-NEXT: .LBB23_2: 404; SPE-NEXT: mr r3, r4 405; SPE-NEXT: blr 406 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"uge", metadata !"fpexcept.strict") #0 407 %res = select i1 %cond, i32 %a, i32 %b 408 ret i32 %res 409} 410 411define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 412; SPE-LABEL: test_f64_ult_s: 413; SPE: # %bb.0: 414; SPE-NEXT: evmergelo r7, r7, r8 415; SPE-NEXT: evmergelo r5, r5, r6 416; SPE-NEXT: efdcmpeq cr0, r5, r5 417; SPE-NEXT: bclr 4, gt, 0 418; SPE-NEXT: # %bb.1: 419; SPE-NEXT: efdcmpeq cr0, r7, r7 420; SPE-NEXT: bclr 4, gt, 0 421; SPE-NEXT: # %bb.2: 422; SPE-NEXT: efdcmplt cr0, r5, r7 423; SPE-NEXT: bclr 12, gt, 0 424; SPE-NEXT: # %bb.3: 425; SPE-NEXT: mr r3, r4 426; SPE-NEXT: blr 427 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ult", metadata !"fpexcept.strict") #0 428 %res = select i1 %cond, i32 %a, i32 %b 429 ret i32 %res 430} 431 432define i32 @test_f64_ule_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 433; SPE-LABEL: test_f64_ule_s: 434; SPE: # %bb.0: 435; SPE-NEXT: evmergelo r7, r7, r8 436; SPE-NEXT: evmergelo r5, r5, r6 437; SPE-NEXT: efdcmpgt cr0, r5, r7 438; SPE-NEXT: bc 12, gt, .LBB25_2 439; SPE-NEXT: # %bb.1: 440; SPE-NEXT: mr r4, r3 441; SPE-NEXT: .LBB25_2: 442; SPE-NEXT: mr r3, r4 443; SPE-NEXT: blr 444 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ule", metadata !"fpexcept.strict") #0 445 %res = select i1 %cond, i32 %a, i32 %b 446 ret i32 %res 447} 448 449define i32 @test_f64_une_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 450; SPE-LABEL: test_f64_une_s: 451; SPE: # %bb.0: 452; SPE-NEXT: evmergelo r7, r7, r8 453; SPE-NEXT: evmergelo r5, r5, r6 454; SPE-NEXT: efdcmpeq cr0, r5, r7 455; SPE-NEXT: bc 12, gt, .LBB26_2 456; SPE-NEXT: # %bb.1: 457; SPE-NEXT: mr r4, r3 458; SPE-NEXT: .LBB26_2: 459; SPE-NEXT: mr r3, r4 460; SPE-NEXT: blr 461 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"une", metadata !"fpexcept.strict") #0 462 %res = select i1 %cond, i32 %a, i32 %b 463 ret i32 %res 464} 465 466define i32 @test_f64_uno_s(i32 %a, i32 %b, double %f1, double %f2) #0 { 467; SPE-LABEL: test_f64_uno_s: 468; SPE: # %bb.0: 469; SPE-NEXT: evmergelo r7, r7, r8 470; SPE-NEXT: evmergelo r5, r5, r6 471; SPE-NEXT: efdcmpeq cr0, r5, r5 472; SPE-NEXT: bclr 4, gt, 0 473; SPE-NEXT: # %bb.1: 474; SPE-NEXT: efdcmpeq cr0, r7, r7 475; SPE-NEXT: bclr 4, gt, 0 476; SPE-NEXT: # %bb.2: 477; SPE-NEXT: mr r3, r4 478; SPE-NEXT: blr 479 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"uno", metadata !"fpexcept.strict") #0 480 %res = select i1 %cond, i32 %a, i32 %b 481 ret i32 %res 482} 483 484attributes #0 = { strictfp nounwind } 485 486declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata) 487declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata) 488