1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \ 3; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s 4; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \ 5; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s 6 7; Function Attrs: nounwind 8define zeroext i8 @_Z6testcff(float %arg) { 9; CHECK-LABEL: _Z6testcff: 10; CHECK: # %bb.0: # %entry 11; CHECK-NEXT: xscvdpsxws f0, f1 12; CHECK-NEXT: stfs f1, -4(r1) 13; CHECK-NEXT: mffprwz r3, f0 14; CHECK-NEXT: blr 15entry: 16 %arg.addr = alloca float, align 4 17 store float %arg, ptr %arg.addr, align 4 18 %0 = load float, ptr %arg.addr, align 4 19 %conv = fptoui float %0 to i8 20 ret i8 %conv 21} 22 23; Function Attrs: nounwind 24define float @_Z6testfcc(i8 zeroext %arg) { 25; CHECK-LABEL: _Z6testfcc: 26; CHECK: # %bb.0: # %entry 27; CHECK-NEXT: mtfprwz f0, r3 28; CHECK-NEXT: stb r3, -1(r1) 29; CHECK-NEXT: xscvuxdsp f1, f0 30; CHECK-NEXT: blr 31entry: 32 %arg.addr = alloca i8, align 1 33 store i8 %arg, ptr %arg.addr, align 1 34 %0 = load i8, ptr %arg.addr, align 1 35 %conv = uitofp i8 %0 to float 36 ret float %conv 37} 38 39; Function Attrs: nounwind 40define zeroext i8 @_Z6testcdd(double %arg) { 41; CHECK-LABEL: _Z6testcdd: 42; CHECK: # %bb.0: # %entry 43; CHECK-NEXT: xscvdpsxws f0, f1 44; CHECK-NEXT: stfd f1, -8(r1) 45; CHECK-NEXT: mffprwz r3, f0 46; CHECK-NEXT: blr 47entry: 48 %arg.addr = alloca double, align 8 49 store double %arg, ptr %arg.addr, align 8 50 %0 = load double, ptr %arg.addr, align 8 51 %conv = fptoui double %0 to i8 52 ret i8 %conv 53} 54 55; Function Attrs: nounwind 56define double @_Z6testdcc(i8 zeroext %arg) { 57; CHECK-LABEL: _Z6testdcc: 58; CHECK: # %bb.0: # %entry 59; CHECK-NEXT: mtfprwz f0, r3 60; CHECK-NEXT: stb r3, -1(r1) 61; CHECK-NEXT: xscvuxddp f1, f0 62; CHECK-NEXT: blr 63entry: 64 %arg.addr = alloca i8, align 1 65 store i8 %arg, ptr %arg.addr, align 1 66 %0 = load i8, ptr %arg.addr, align 1 67 %conv = uitofp i8 %0 to double 68 ret double %conv 69} 70 71; Function Attrs: nounwind 72define zeroext i8 @_Z7testucff(float %arg) { 73; CHECK-LABEL: _Z7testucff: 74; CHECK: # %bb.0: # %entry 75; CHECK-NEXT: xscvdpsxws f0, f1 76; CHECK-NEXT: stfs f1, -4(r1) 77; CHECK-NEXT: mffprwz r3, f0 78; CHECK-NEXT: blr 79entry: 80 %arg.addr = alloca float, align 4 81 store float %arg, ptr %arg.addr, align 4 82 %0 = load float, ptr %arg.addr, align 4 83 %conv = fptoui float %0 to i8 84 ret i8 %conv 85} 86 87; Function Attrs: nounwind 88define float @_Z7testfuch(i8 zeroext %arg) { 89; CHECK-LABEL: _Z7testfuch: 90; CHECK: # %bb.0: # %entry 91; CHECK-NEXT: mtfprwz f0, r3 92; CHECK-NEXT: stb r3, -1(r1) 93; CHECK-NEXT: xscvuxdsp f1, f0 94; CHECK-NEXT: blr 95entry: 96 %arg.addr = alloca i8, align 1 97 store i8 %arg, ptr %arg.addr, align 1 98 %0 = load i8, ptr %arg.addr, align 1 99 %conv = uitofp i8 %0 to float 100 ret float %conv 101} 102 103; Function Attrs: nounwind 104define zeroext i8 @_Z7testucdd(double %arg) { 105; CHECK-LABEL: _Z7testucdd: 106; CHECK: # %bb.0: # %entry 107; CHECK-NEXT: xscvdpsxws f0, f1 108; CHECK-NEXT: stfd f1, -8(r1) 109; CHECK-NEXT: mffprwz r3, f0 110; CHECK-NEXT: blr 111entry: 112 %arg.addr = alloca double, align 8 113 store double %arg, ptr %arg.addr, align 8 114 %0 = load double, ptr %arg.addr, align 8 115 %conv = fptoui double %0 to i8 116 ret i8 %conv 117} 118 119; Function Attrs: nounwind 120define double @_Z7testduch(i8 zeroext %arg) { 121; CHECK-LABEL: _Z7testduch: 122; CHECK: # %bb.0: # %entry 123; CHECK-NEXT: mtfprwz f0, r3 124; CHECK-NEXT: stb r3, -1(r1) 125; CHECK-NEXT: xscvuxddp f1, f0 126; CHECK-NEXT: blr 127entry: 128 %arg.addr = alloca i8, align 1 129 store i8 %arg, ptr %arg.addr, align 1 130 %0 = load i8, ptr %arg.addr, align 1 131 %conv = uitofp i8 %0 to double 132 ret double %conv 133} 134 135; Function Attrs: nounwind 136define signext i16 @_Z6testsff(float %arg) { 137; CHECK-LABEL: _Z6testsff: 138; CHECK: # %bb.0: # %entry 139; CHECK-NEXT: xscvdpsxws f0, f1 140; CHECK-NEXT: stfs f1, -4(r1) 141; CHECK-NEXT: mffprwz r3, f0 142; CHECK-NEXT: extsw r3, r3 143; CHECK-NEXT: blr 144entry: 145 %arg.addr = alloca float, align 4 146 store float %arg, ptr %arg.addr, align 4 147 %0 = load float, ptr %arg.addr, align 4 148 %conv = fptosi float %0 to i16 149 ret i16 %conv 150} 151 152; Function Attrs: nounwind 153define float @_Z6testfss(i16 signext %arg) { 154; CHECK-LABEL: _Z6testfss: 155; CHECK: # %bb.0: # %entry 156; CHECK-NEXT: mtfprwa f0, r3 157; CHECK-NEXT: sth r3, -2(r1) 158; CHECK-NEXT: xscvsxdsp f1, f0 159; CHECK-NEXT: blr 160entry: 161 %arg.addr = alloca i16, align 2 162 store i16 %arg, ptr %arg.addr, align 2 163 %0 = load i16, ptr %arg.addr, align 2 164 %conv = sitofp i16 %0 to float 165 ret float %conv 166} 167 168; Function Attrs: nounwind 169define signext i16 @_Z6testsdd(double %arg) { 170; CHECK-LABEL: _Z6testsdd: 171; CHECK: # %bb.0: # %entry 172; CHECK-NEXT: xscvdpsxws f0, f1 173; CHECK-NEXT: stfd f1, -8(r1) 174; CHECK-NEXT: mffprwz r3, f0 175; CHECK-NEXT: extsw r3, r3 176; CHECK-NEXT: blr 177entry: 178 %arg.addr = alloca double, align 8 179 store double %arg, ptr %arg.addr, align 8 180 %0 = load double, ptr %arg.addr, align 8 181 %conv = fptosi double %0 to i16 182 ret i16 %conv 183} 184 185; Function Attrs: nounwind 186define double @_Z6testdss(i16 signext %arg) { 187; CHECK-LABEL: _Z6testdss: 188; CHECK: # %bb.0: # %entry 189; CHECK-NEXT: mtfprwa f0, r3 190; CHECK-NEXT: sth r3, -2(r1) 191; CHECK-NEXT: xscvsxddp f1, f0 192; CHECK-NEXT: blr 193entry: 194 %arg.addr = alloca i16, align 2 195 store i16 %arg, ptr %arg.addr, align 2 196 %0 = load i16, ptr %arg.addr, align 2 197 %conv = sitofp i16 %0 to double 198 ret double %conv 199} 200 201; Function Attrs: nounwind 202define zeroext i16 @_Z7testusff(float %arg) { 203; CHECK-LABEL: _Z7testusff: 204; CHECK: # %bb.0: # %entry 205; CHECK-NEXT: xscvdpsxws f0, f1 206; CHECK-NEXT: stfs f1, -4(r1) 207; CHECK-NEXT: mffprwz r3, f0 208; CHECK-NEXT: blr 209entry: 210 %arg.addr = alloca float, align 4 211 store float %arg, ptr %arg.addr, align 4 212 %0 = load float, ptr %arg.addr, align 4 213 %conv = fptoui float %0 to i16 214 ret i16 %conv 215} 216 217; Function Attrs: nounwind 218define float @_Z7testfust(i16 zeroext %arg) { 219; CHECK-LABEL: _Z7testfust: 220; CHECK: # %bb.0: # %entry 221; CHECK-NEXT: mtfprwz f0, r3 222; CHECK-NEXT: sth r3, -2(r1) 223; CHECK-NEXT: xscvuxdsp f1, f0 224; CHECK-NEXT: blr 225entry: 226 %arg.addr = alloca i16, align 2 227 store i16 %arg, ptr %arg.addr, align 2 228 %0 = load i16, ptr %arg.addr, align 2 229 %conv = uitofp i16 %0 to float 230 ret float %conv 231} 232 233; Function Attrs: nounwind 234define zeroext i16 @_Z7testusdd(double %arg) { 235; CHECK-LABEL: _Z7testusdd: 236; CHECK: # %bb.0: # %entry 237; CHECK-NEXT: xscvdpsxws f0, f1 238; CHECK-NEXT: stfd f1, -8(r1) 239; CHECK-NEXT: mffprwz r3, f0 240; CHECK-NEXT: blr 241entry: 242 %arg.addr = alloca double, align 8 243 store double %arg, ptr %arg.addr, align 8 244 %0 = load double, ptr %arg.addr, align 8 245 %conv = fptoui double %0 to i16 246 ret i16 %conv 247} 248 249; Function Attrs: nounwind 250define double @_Z7testdust(i16 zeroext %arg) { 251; CHECK-LABEL: _Z7testdust: 252; CHECK: # %bb.0: # %entry 253; CHECK-NEXT: mtfprwz f0, r3 254; CHECK-NEXT: sth r3, -2(r1) 255; CHECK-NEXT: xscvuxddp f1, f0 256; CHECK-NEXT: blr 257entry: 258 %arg.addr = alloca i16, align 2 259 store i16 %arg, ptr %arg.addr, align 2 260 %0 = load i16, ptr %arg.addr, align 2 261 %conv = uitofp i16 %0 to double 262 ret double %conv 263} 264 265; Function Attrs: nounwind 266define signext i32 @_Z6testiff(float %arg) { 267; CHECK-LABEL: _Z6testiff: 268; CHECK: # %bb.0: # %entry 269; CHECK-NEXT: xscvdpsxws f0, f1 270; CHECK-NEXT: stfs f1, -4(r1) 271; CHECK-NEXT: mffprwz r3, f0 272; CHECK-NEXT: extsw r3, r3 273; CHECK-NEXT: blr 274entry: 275 %arg.addr = alloca float, align 4 276 store float %arg, ptr %arg.addr, align 4 277 %0 = load float, ptr %arg.addr, align 4 278 %conv = fptosi float %0 to i32 279 ret i32 %conv 280} 281 282; Function Attrs: nounwind 283define float @_Z6testfii(i32 signext %arg) { 284; CHECK-LABEL: _Z6testfii: 285; CHECK: # %bb.0: # %entry 286; CHECK-NEXT: mtfprwa f0, r3 287; CHECK-NEXT: stw r3, -4(r1) 288; CHECK-NEXT: xscvsxdsp f1, f0 289; CHECK-NEXT: blr 290entry: 291 %arg.addr = alloca i32, align 4 292 store i32 %arg, ptr %arg.addr, align 4 293 %0 = load i32, ptr %arg.addr, align 4 294 %conv = sitofp i32 %0 to float 295 ret float %conv 296} 297 298; Function Attrs: nounwind 299define signext i32 @_Z6testidd(double %arg) { 300; CHECK-LABEL: _Z6testidd: 301; CHECK: # %bb.0: # %entry 302; CHECK-NEXT: xscvdpsxws f0, f1 303; CHECK-NEXT: stfd f1, -8(r1) 304; CHECK-NEXT: mffprwz r3, f0 305; CHECK-NEXT: extsw r3, r3 306; CHECK-NEXT: blr 307entry: 308 %arg.addr = alloca double, align 8 309 store double %arg, ptr %arg.addr, align 8 310 %0 = load double, ptr %arg.addr, align 8 311 %conv = fptosi double %0 to i32 312 ret i32 %conv 313} 314 315; Function Attrs: nounwind 316define double @_Z6testdii(i32 signext %arg) { 317; CHECK-LABEL: _Z6testdii: 318; CHECK: # %bb.0: # %entry 319; CHECK-NEXT: mtfprwa f0, r3 320; CHECK-NEXT: stw r3, -4(r1) 321; CHECK-NEXT: xscvsxddp f1, f0 322; CHECK-NEXT: blr 323entry: 324 %arg.addr = alloca i32, align 4 325 store i32 %arg, ptr %arg.addr, align 4 326 %0 = load i32, ptr %arg.addr, align 4 327 %conv = sitofp i32 %0 to double 328 ret double %conv 329} 330 331; Function Attrs: nounwind 332define zeroext i32 @_Z7testuiff(float %arg) { 333; CHECK-LABEL: _Z7testuiff: 334; CHECK: # %bb.0: # %entry 335; CHECK-NEXT: xscvdpuxws f0, f1 336; CHECK-NEXT: stfs f1, -4(r1) 337; CHECK-NEXT: mffprwz r3, f0 338; CHECK-NEXT: blr 339entry: 340 %arg.addr = alloca float, align 4 341 store float %arg, ptr %arg.addr, align 4 342 %0 = load float, ptr %arg.addr, align 4 343 %conv = fptoui float %0 to i32 344 ret i32 %conv 345} 346 347; Function Attrs: nounwind 348define float @_Z7testfuij(i32 zeroext %arg) { 349; CHECK-LABEL: _Z7testfuij: 350; CHECK: # %bb.0: # %entry 351; CHECK-NEXT: mtfprwz f0, r3 352; CHECK-NEXT: stw r3, -4(r1) 353; CHECK-NEXT: xscvuxdsp f1, f0 354; CHECK-NEXT: blr 355entry: 356 %arg.addr = alloca i32, align 4 357 store i32 %arg, ptr %arg.addr, align 4 358 %0 = load i32, ptr %arg.addr, align 4 359 %conv = uitofp i32 %0 to float 360 ret float %conv 361} 362 363; Function Attrs: nounwind 364define zeroext i32 @_Z7testuidd(double %arg) { 365; CHECK-LABEL: _Z7testuidd: 366; CHECK: # %bb.0: # %entry 367; CHECK-NEXT: xscvdpuxws f0, f1 368; CHECK-NEXT: stfd f1, -8(r1) 369; CHECK-NEXT: mffprwz r3, f0 370; CHECK-NEXT: blr 371entry: 372 %arg.addr = alloca double, align 8 373 store double %arg, ptr %arg.addr, align 8 374 %0 = load double, ptr %arg.addr, align 8 375 %conv = fptoui double %0 to i32 376 ret i32 %conv 377} 378 379; Function Attrs: nounwind 380define double @_Z7testduij(i32 zeroext %arg) { 381; CHECK-LABEL: _Z7testduij: 382; CHECK: # %bb.0: # %entry 383; CHECK-NEXT: mtfprwz f0, r3 384; CHECK-NEXT: stw r3, -4(r1) 385; CHECK-NEXT: xscvuxddp f1, f0 386; CHECK-NEXT: blr 387entry: 388 %arg.addr = alloca i32, align 4 389 store i32 %arg, ptr %arg.addr, align 4 390 %0 = load i32, ptr %arg.addr, align 4 391 %conv = uitofp i32 %0 to double 392 ret double %conv 393} 394 395; Function Attrs: nounwind 396define i64 @_Z7testllff(float %arg) { 397; CHECK-LABEL: _Z7testllff: 398; CHECK: # %bb.0: # %entry 399; CHECK-NEXT: xscvdpsxds f0, f1 400; CHECK-NEXT: stfs f1, -4(r1) 401; CHECK-NEXT: mffprd r3, f0 402; CHECK-NEXT: blr 403entry: 404 %arg.addr = alloca float, align 4 405 store float %arg, ptr %arg.addr, align 4 406 %0 = load float, ptr %arg.addr, align 4 407 %conv = fptosi float %0 to i64 408 ret i64 %conv 409} 410 411; Function Attrs: nounwind 412define float @_Z7testfllx(i64 %arg) { 413; CHECK-LABEL: _Z7testfllx: 414; CHECK: # %bb.0: # %entry 415; CHECK-NEXT: mtfprd f0, r3 416; CHECK-NEXT: std r3, -8(r1) 417; CHECK-NEXT: xscvsxdsp f1, f0 418; CHECK-NEXT: blr 419entry: 420 %arg.addr = alloca i64, align 8 421 store i64 %arg, ptr %arg.addr, align 8 422 %0 = load i64, ptr %arg.addr, align 8 423 %conv = sitofp i64 %0 to float 424 ret float %conv 425} 426 427; Function Attrs: nounwind 428define i64 @_Z7testlldd(double %arg) { 429; CHECK-LABEL: _Z7testlldd: 430; CHECK: # %bb.0: # %entry 431; CHECK-NEXT: xscvdpsxds f0, f1 432; CHECK-NEXT: stfd f1, -8(r1) 433; CHECK-NEXT: mffprd r3, f0 434; CHECK-NEXT: blr 435entry: 436 %arg.addr = alloca double, align 8 437 store double %arg, ptr %arg.addr, align 8 438 %0 = load double, ptr %arg.addr, align 8 439 %conv = fptosi double %0 to i64 440 ret i64 %conv 441} 442 443; Function Attrs: nounwind 444define double @_Z7testdllx(i64 %arg) { 445; CHECK-LABEL: _Z7testdllx: 446; CHECK: # %bb.0: # %entry 447; CHECK-NEXT: mtfprd f0, r3 448; CHECK-NEXT: std r3, -8(r1) 449; CHECK-NEXT: xscvsxddp f1, f0 450; CHECK-NEXT: blr 451entry: 452 %arg.addr = alloca i64, align 8 453 store i64 %arg, ptr %arg.addr, align 8 454 %0 = load i64, ptr %arg.addr, align 8 455 %conv = sitofp i64 %0 to double 456 ret double %conv 457} 458 459; Function Attrs: nounwind 460define i64 @_Z8testullff(float %arg) { 461; CHECK-LABEL: _Z8testullff: 462; CHECK: # %bb.0: # %entry 463; CHECK-NEXT: xscvdpuxds f0, f1 464; CHECK-NEXT: stfs f1, -4(r1) 465; CHECK-NEXT: mffprd r3, f0 466; CHECK-NEXT: blr 467entry: 468 %arg.addr = alloca float, align 4 469 store float %arg, ptr %arg.addr, align 4 470 %0 = load float, ptr %arg.addr, align 4 471 %conv = fptoui float %0 to i64 472 ret i64 %conv 473} 474 475; Function Attrs: nounwind 476define float @_Z8testfully(i64 %arg) { 477; CHECK-LABEL: _Z8testfully: 478; CHECK: # %bb.0: # %entry 479; CHECK-NEXT: mtfprd f0, r3 480; CHECK-NEXT: std r3, -8(r1) 481; CHECK-NEXT: xscvuxdsp f1, f0 482; CHECK-NEXT: blr 483entry: 484 %arg.addr = alloca i64, align 8 485 store i64 %arg, ptr %arg.addr, align 8 486 %0 = load i64, ptr %arg.addr, align 8 487 %conv = uitofp i64 %0 to float 488 ret float %conv 489} 490 491; Function Attrs: nounwind 492define i64 @_Z8testulldd(double %arg) { 493; CHECK-LABEL: _Z8testulldd: 494; CHECK: # %bb.0: # %entry 495; CHECK-NEXT: xscvdpuxds f0, f1 496; CHECK-NEXT: stfd f1, -8(r1) 497; CHECK-NEXT: mffprd r3, f0 498; CHECK-NEXT: blr 499entry: 500 %arg.addr = alloca double, align 8 501 store double %arg, ptr %arg.addr, align 8 502 %0 = load double, ptr %arg.addr, align 8 503 %conv = fptoui double %0 to i64 504 ret i64 %conv 505} 506 507; Function Attrs: nounwind 508define double @_Z8testdully(i64 %arg) { 509; CHECK-LABEL: _Z8testdully: 510; CHECK: # %bb.0: # %entry 511; CHECK-NEXT: mtfprd f0, r3 512; CHECK-NEXT: std r3, -8(r1) 513; CHECK-NEXT: xscvuxddp f1, f0 514; CHECK-NEXT: blr 515entry: 516 %arg.addr = alloca i64, align 8 517 store i64 %arg, ptr %arg.addr, align 8 518 %0 = load i64, ptr %arg.addr, align 8 519 %conv = uitofp i64 %0 to double 520 ret double %conv 521} 522