xref: /llvm-project/llvm/test/CodeGen/PowerPC/fma-assoc.ll (revision a51712751c184ebe056718c938d2526693a31564) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -fp-contract=fast \
3; RUN:   -mcpu=ppc -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
4; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff -fp-contract=fast \
5; RUN:   -mcpu=ppc -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
6; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
7; RUN:   -fp-contract=fast -mattr=+vsx -disable-ppc-vsx-fma-mutation=false \
8; RUN:   -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s
9; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \
10; RUN:   -fp-contract=fast -mattr=+vsx -disable-ppc-vsx-fma-mutation=false \
11; RUN:   -mcpu=pwr7 -vec-extabi | FileCheck -check-prefix=CHECK-VSX %s
12; RUN: llc -verify-machineinstrs < %s -mtriple=powerpcspe-linux-unknown-gnu \
13; RUN:   | FileCheck -check-prefix=CHECK-SPE %s
14
15define double @test_FMADD_ASSOC1(double %A, double %B, double %C,
16; CHECK-LABEL: test_FMADD_ASSOC1:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    fmul 0, 3, 4
19; CHECK-NEXT:    fmadd 0, 1, 2, 0
20; CHECK-NEXT:    fadd 1, 0, 5
21; CHECK-NEXT:    blr
22;
23; CHECK-VSX-LABEL: test_FMADD_ASSOC1:
24; CHECK-VSX:       # %bb.0:
25; CHECK-VSX-NEXT:    xsmuldp 0, 3, 4
26; CHECK-VSX-NEXT:    xsmaddadp 0, 1, 2
27; CHECK-VSX-NEXT:    xsadddp 1, 0, 5
28; CHECK-VSX-NEXT:    blr
29;
30; CHECK-SPE-LABEL: test_FMADD_ASSOC1:
31; CHECK-SPE:       # %bb.0:
32; CHECK-SPE-NEXT:    evmergelo 9, 9, 10
33; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
34; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
35; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
36; CHECK-SPE-NEXT:    efdmul 4, 7, 9
37; CHECK-SPE-NEXT:    efdmul 3, 3, 5
38; CHECK-SPE-NEXT:    evldd 5, 8(1)
39; CHECK-SPE-NEXT:    efdadd 3, 3, 4
40; CHECK-SPE-NEXT:    efdadd 4, 3, 5
41; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
42; CHECK-SPE-NEXT:    blr
43                                 double %D, double %E) {
44  %F = fmul double %A, %B         ; <double> [#uses=1]
45  %G = fmul double %C, %D         ; <double> [#uses=1]
46  %H = fadd double %F, %G         ; <double> [#uses=1]
47  %I = fadd double %H, %E         ; <double> [#uses=1]
48  ret double %I
49}
50
51define double @test_FMADD_ASSOC2(double %A, double %B, double %C,
52; CHECK-LABEL: test_FMADD_ASSOC2:
53; CHECK:       # %bb.0:
54; CHECK-NEXT:    fmul 0, 3, 4
55; CHECK-NEXT:    fmadd 0, 1, 2, 0
56; CHECK-NEXT:    fadd 1, 5, 0
57; CHECK-NEXT:    blr
58;
59; CHECK-VSX-LABEL: test_FMADD_ASSOC2:
60; CHECK-VSX:       # %bb.0:
61; CHECK-VSX-NEXT:    xsmuldp 0, 3, 4
62; CHECK-VSX-NEXT:    xsmaddadp 0, 1, 2
63; CHECK-VSX-NEXT:    xsadddp 1, 5, 0
64; CHECK-VSX-NEXT:    blr
65;
66; CHECK-SPE-LABEL: test_FMADD_ASSOC2:
67; CHECK-SPE:       # %bb.0:
68; CHECK-SPE-NEXT:    evmergelo 9, 9, 10
69; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
70; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
71; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
72; CHECK-SPE-NEXT:    efdmul 4, 7, 9
73; CHECK-SPE-NEXT:    efdmul 3, 3, 5
74; CHECK-SPE-NEXT:    evldd 5, 8(1)
75; CHECK-SPE-NEXT:    efdadd 3, 3, 4
76; CHECK-SPE-NEXT:    efdadd 4, 5, 3
77; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
78; CHECK-SPE-NEXT:    blr
79                                 double %D, double %E) {
80  %F = fmul double %A, %B         ; <double> [#uses=1]
81  %G = fmul double %C, %D         ; <double> [#uses=1]
82  %H = fadd double %F, %G         ; <double> [#uses=1]
83  %I = fadd double %E, %H         ; <double> [#uses=1]
84  ret double %I
85}
86
87define double @test_FMSUB_ASSOC1(double %A, double %B, double %C,
88; CHECK-LABEL: test_FMSUB_ASSOC1:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    fmul 0, 3, 4
91; CHECK-NEXT:    fmadd 0, 1, 2, 0
92; CHECK-NEXT:    fsub 1, 0, 5
93; CHECK-NEXT:    blr
94;
95; CHECK-VSX-LABEL: test_FMSUB_ASSOC1:
96; CHECK-VSX:       # %bb.0:
97; CHECK-VSX-NEXT:    xsmuldp 0, 3, 4
98; CHECK-VSX-NEXT:    xsmaddadp 0, 1, 2
99; CHECK-VSX-NEXT:    xssubdp 1, 0, 5
100; CHECK-VSX-NEXT:    blr
101;
102; CHECK-SPE-LABEL: test_FMSUB_ASSOC1:
103; CHECK-SPE:       # %bb.0:
104; CHECK-SPE-NEXT:    evmergelo 9, 9, 10
105; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
106; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
107; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
108; CHECK-SPE-NEXT:    efdmul 4, 7, 9
109; CHECK-SPE-NEXT:    efdmul 3, 3, 5
110; CHECK-SPE-NEXT:    evldd 5, 8(1)
111; CHECK-SPE-NEXT:    efdadd 3, 3, 4
112; CHECK-SPE-NEXT:    efdsub 4, 3, 5
113; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
114; CHECK-SPE-NEXT:    blr
115                                 double %D, double %E) {
116  %F = fmul double %A, %B         ; <double> [#uses=1]
117  %G = fmul double %C, %D         ; <double> [#uses=1]
118  %H = fadd double %F, %G         ; <double> [#uses=1]
119  %I = fsub double %H, %E         ; <double> [#uses=1]
120  ret double %I
121}
122
123define double @test_FMSUB_ASSOC2(double %A, double %B, double %C,
124; CHECK-LABEL: test_FMSUB_ASSOC2:
125; CHECK:       # %bb.0:
126; CHECK-NEXT:    fmul 0, 3, 4
127; CHECK-NEXT:    fmadd 0, 1, 2, 0
128; CHECK-NEXT:    fsub 1, 5, 0
129; CHECK-NEXT:    blr
130;
131; CHECK-VSX-LABEL: test_FMSUB_ASSOC2:
132; CHECK-VSX:       # %bb.0:
133; CHECK-VSX-NEXT:    xsmuldp 0, 3, 4
134; CHECK-VSX-NEXT:    xsmaddadp 0, 1, 2
135; CHECK-VSX-NEXT:    xssubdp 1, 5, 0
136; CHECK-VSX-NEXT:    blr
137;
138; CHECK-SPE-LABEL: test_FMSUB_ASSOC2:
139; CHECK-SPE:       # %bb.0:
140; CHECK-SPE-NEXT:    evmergelo 9, 9, 10
141; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
142; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
143; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
144; CHECK-SPE-NEXT:    efdmul 4, 7, 9
145; CHECK-SPE-NEXT:    efdmul 3, 3, 5
146; CHECK-SPE-NEXT:    evldd 5, 8(1)
147; CHECK-SPE-NEXT:    efdadd 3, 3, 4
148; CHECK-SPE-NEXT:    efdsub 4, 5, 3
149; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
150; CHECK-SPE-NEXT:    blr
151                                 double %D, double %E) {
152  %F = fmul double %A, %B         ; <double> [#uses=1]
153  %G = fmul double %C, %D         ; <double> [#uses=1]
154  %H = fadd double %F, %G         ; <double> [#uses=1]
155  %I = fsub double %E, %H         ; <double> [#uses=1]
156  ret double %I
157}
158
159define double @test_FMADD_ASSOC_EXT1(float %A, float %B, double %C,
160; CHECK-LABEL: test_FMADD_ASSOC_EXT1:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    fmadd 0, 1, 2, 5
163; CHECK-NEXT:    fmadd 1, 3, 4, 0
164; CHECK-NEXT:    blr
165;
166; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT1:
167; CHECK-VSX:       # %bb.0:
168; CHECK-VSX-NEXT:    xsmaddmdp 1, 2, 5
169; CHECK-VSX-NEXT:    xsmaddadp 1, 3, 4
170; CHECK-VSX-NEXT:    blr
171;
172; CHECK-SPE-LABEL: test_FMADD_ASSOC_EXT1:
173; CHECK-SPE:       # %bb.0:
174; CHECK-SPE-NEXT:    efsmul 3, 3, 4
175; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
176; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
177; CHECK-SPE-NEXT:    efdcfs 3, 3
178; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
179; CHECK-SPE-NEXT:    efdmul 5, 5, 7
180; CHECK-SPE-NEXT:    efdadd 3, 5, 3
181; CHECK-SPE-NEXT:    efdadd 4, 3, 4
182; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
183; CHECK-SPE-NEXT:    blr
184                                 double %D, double %E) {
185  %F = fmul float %A, %B         ; <float> [#uses=1]
186  %G = fpext float %F to double   ; <double> [#uses=1]
187  %H = fmul double %C, %D         ; <double> [#uses=1]
188  %I = fadd double %H, %G         ; <double> [#uses=1]
189  %J = fadd double %I, %E         ; <double> [#uses=1]
190  ret double %J
191}
192
193define double @test_FMADD_ASSOC_EXT2(float %A, float %B, float %C,
194; CHECK-LABEL: test_FMADD_ASSOC_EXT2:
195; CHECK:       # %bb.0:
196; CHECK-NEXT:    fmadd 0, 3, 4, 5
197; CHECK-NEXT:    fmadd 1, 1, 2, 0
198; CHECK-NEXT:    blr
199;
200; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT2:
201; CHECK-VSX:       # %bb.0:
202; CHECK-VSX-NEXT:    xsmaddmdp 3, 4, 5
203; CHECK-VSX-NEXT:    xsmaddadp 3, 1, 2
204; CHECK-VSX-NEXT:    fmr 1, 3
205; CHECK-VSX-NEXT:    blr
206;
207; CHECK-SPE-LABEL: test_FMADD_ASSOC_EXT2:
208; CHECK-SPE:       # %bb.0:
209; CHECK-SPE-NEXT:    efsmul 3, 3, 4
210; CHECK-SPE-NEXT:    efsmul 4, 5, 6
211; CHECK-SPE-NEXT:    efsadd 3, 3, 4
212; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
213; CHECK-SPE-NEXT:    efdcfs 3, 3
214; CHECK-SPE-NEXT:    efdadd 4, 3, 4
215; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
216; CHECK-SPE-NEXT:    blr
217                                 float %D, double %E) {
218  %F = fmul float %A, %B         ; <float> [#uses=1]
219  %G = fmul float %C, %D         ; <float> [#uses=1]
220  %H = fadd float %F, %G         ; <float> [#uses=1]
221  %I = fpext float %H to double   ; <double> [#uses=1]
222  %J = fadd double %I, %E         ; <double> [#uses=1]
223  ret double %J
224}
225
226define double @test_FMADD_ASSOC_EXT3(float %A, float %B, double %C,
227; CHECK-LABEL: test_FMADD_ASSOC_EXT3:
228; CHECK:       # %bb.0:
229; CHECK-NEXT:    fmadd 0, 1, 2, 5
230; CHECK-NEXT:    fmadd 1, 3, 4, 0
231; CHECK-NEXT:    blr
232;
233; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT3:
234; CHECK-VSX:       # %bb.0:
235; CHECK-VSX-NEXT:    xsmaddmdp 1, 2, 5
236; CHECK-VSX-NEXT:    xsmaddadp 1, 3, 4
237; CHECK-VSX-NEXT:    blr
238;
239; CHECK-SPE-LABEL: test_FMADD_ASSOC_EXT3:
240; CHECK-SPE:       # %bb.0:
241; CHECK-SPE-NEXT:    efsmul 3, 3, 4
242; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
243; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
244; CHECK-SPE-NEXT:    efdcfs 3, 3
245; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
246; CHECK-SPE-NEXT:    efdmul 5, 5, 7
247; CHECK-SPE-NEXT:    efdadd 3, 5, 3
248; CHECK-SPE-NEXT:    efdadd 4, 4, 3
249; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
250; CHECK-SPE-NEXT:    blr
251                                 double %D, double %E) {
252  %F = fmul float %A, %B          ; <float> [#uses=1]
253  %G = fpext float %F to double   ; <double> [#uses=1]
254  %H = fmul double %C, %D         ; <double> [#uses=1]
255  %I = fadd double %H, %G         ; <double> [#uses=1]
256  %J = fadd double %E, %I         ; <double> [#uses=1]
257  ret double %J
258}
259
260define double @test_FMADD_ASSOC_EXT4(float %A, float %B, float %C,
261; CHECK-LABEL: test_FMADD_ASSOC_EXT4:
262; CHECK:       # %bb.0:
263; CHECK-NEXT:    fmadd 0, 3, 4, 5
264; CHECK-NEXT:    fmadd 1, 1, 2, 0
265; CHECK-NEXT:    blr
266;
267; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT4:
268; CHECK-VSX:       # %bb.0:
269; CHECK-VSX-NEXT:    xsmaddmdp 3, 4, 5
270; CHECK-VSX-NEXT:    xsmaddadp 3, 1, 2
271; CHECK-VSX-NEXT:    fmr 1, 3
272; CHECK-VSX-NEXT:    blr
273;
274; CHECK-SPE-LABEL: test_FMADD_ASSOC_EXT4:
275; CHECK-SPE:       # %bb.0:
276; CHECK-SPE-NEXT:    efsmul 3, 3, 4
277; CHECK-SPE-NEXT:    efsmul 4, 5, 6
278; CHECK-SPE-NEXT:    efsadd 3, 3, 4
279; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
280; CHECK-SPE-NEXT:    efdcfs 3, 3
281; CHECK-SPE-NEXT:    efdadd 4, 4, 3
282; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
283; CHECK-SPE-NEXT:    blr
284                                 float %D, double %E) {
285  %F = fmul float %A, %B          ; <float> [#uses=1]
286  %G = fmul float %C, %D          ; <float> [#uses=1]
287  %H = fadd float %F, %G          ; <float> [#uses=1]
288  %I = fpext float %H to double   ; <double> [#uses=1]
289  %J = fadd double %E, %I         ; <double> [#uses=1]
290  ret double %J
291}
292
293define double @test_FMSUB_ASSOC_EXT1(float %A, float %B, double %C,
294; CHECK-LABEL: test_FMSUB_ASSOC_EXT1:
295; CHECK:       # %bb.0:
296; CHECK-NEXT:    fmuls 0, 1, 2
297; CHECK-NEXT:    fmadd 0, 3, 4, 0
298; CHECK-NEXT:    fsub 1, 0, 5
299; CHECK-NEXT:    blr
300;
301; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT1:
302; CHECK-VSX:       # %bb.0:
303; CHECK-VSX-NEXT:    fmuls 0, 1, 2
304; CHECK-VSX-NEXT:    xsmaddadp 0, 3, 4
305; CHECK-VSX-NEXT:    xssubdp 1, 0, 5
306; CHECK-VSX-NEXT:    blr
307;
308; CHECK-SPE-LABEL: test_FMSUB_ASSOC_EXT1:
309; CHECK-SPE:       # %bb.0:
310; CHECK-SPE-NEXT:    efsmul 3, 3, 4
311; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
312; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
313; CHECK-SPE-NEXT:    efdcfs 3, 3
314; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
315; CHECK-SPE-NEXT:    efdmul 5, 5, 7
316; CHECK-SPE-NEXT:    efdadd 3, 5, 3
317; CHECK-SPE-NEXT:    efdsub 4, 3, 4
318; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
319; CHECK-SPE-NEXT:    blr
320                                 double %D, double %E) {
321  %F = fmul float %A, %B          ; <float> [#uses=1]
322  %G = fpext float %F to double   ; <double> [#uses=1]
323  %H = fmul double %C, %D         ; <double> [#uses=1]
324  %I = fadd double %H, %G         ; <double> [#uses=1]
325  %J = fsub double %I, %E         ; <double> [#uses=1]
326  ret double %J
327}
328
329define double @test_FMSUB_ASSOC_EXT2(float %A, float %B, float %C,
330; CHECK-LABEL: test_FMSUB_ASSOC_EXT2:
331; CHECK:       # %bb.0:
332; CHECK-NEXT:    fmuls 0, 3, 4
333; CHECK-NEXT:    fmadds 0, 1, 2, 0
334; CHECK-NEXT:    fsub 1, 0, 5
335; CHECK-NEXT:    blr
336;
337; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT2:
338; CHECK-VSX:       # %bb.0:
339; CHECK-VSX-NEXT:    fmuls 0, 3, 4
340; CHECK-VSX-NEXT:    fmadds 0, 1, 2, 0
341; CHECK-VSX-NEXT:    xssubdp 1, 0, 5
342; CHECK-VSX-NEXT:    blr
343;
344; CHECK-SPE-LABEL: test_FMSUB_ASSOC_EXT2:
345; CHECK-SPE:       # %bb.0:
346; CHECK-SPE-NEXT:    efsmul 3, 3, 4
347; CHECK-SPE-NEXT:    efsmul 4, 5, 6
348; CHECK-SPE-NEXT:    efsadd 3, 3, 4
349; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
350; CHECK-SPE-NEXT:    efdcfs 3, 3
351; CHECK-SPE-NEXT:    efdsub 4, 3, 4
352; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
353; CHECK-SPE-NEXT:    blr
354                                 float %D, double %E) {
355  %F = fmul float %A, %B          ; <float> [#uses=1]
356  %G = fmul float %C, %D          ; <float> [#uses=1]
357  %H = fadd float %F, %G          ; <float> [#uses=1]
358  %I = fpext float %H to double   ; <double> [#uses=1]
359  %J = fsub double %I, %E         ; <double> [#uses=1]
360  ret double %J
361}
362
363define double @test_FMSUB_ASSOC_EXT3(float %A, float %B, double %C,
364; CHECK-LABEL: test_FMSUB_ASSOC_EXT3:
365; CHECK:       # %bb.0:
366; CHECK-NEXT:    fmuls 0, 1, 2
367; CHECK-NEXT:    fmadd 0, 3, 4, 0
368; CHECK-NEXT:    fsub 1, 5, 0
369; CHECK-NEXT:    blr
370;
371; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT3:
372; CHECK-VSX:       # %bb.0:
373; CHECK-VSX-NEXT:    fmuls 0, 1, 2
374; CHECK-VSX-NEXT:    xsmaddadp 0, 3, 4
375; CHECK-VSX-NEXT:    xssubdp 1, 5, 0
376; CHECK-VSX-NEXT:    blr
377;
378; CHECK-SPE-LABEL: test_FMSUB_ASSOC_EXT3:
379; CHECK-SPE:       # %bb.0:
380; CHECK-SPE-NEXT:    efsmul 3, 3, 4
381; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
382; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
383; CHECK-SPE-NEXT:    efdcfs 3, 3
384; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
385; CHECK-SPE-NEXT:    efdmul 5, 5, 7
386; CHECK-SPE-NEXT:    efdadd 3, 5, 3
387; CHECK-SPE-NEXT:    efdsub 4, 4, 3
388; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
389; CHECK-SPE-NEXT:    blr
390                                 double %D, double %E) {
391  %F = fmul float %A, %B          ; <float> [#uses=1]
392  %G = fpext float %F to double   ; <double> [#uses=1]
393  %H = fmul double %C, %D         ; <double> [#uses=1]
394  %I = fadd double %H, %G         ; <double> [#uses=1]
395  %J = fsub double %E, %I         ; <double> [#uses=1]
396  ret double %J
397}
398
399define double @test_FMSUB_ASSOC_EXT4(float %A, float %B, float %C,
400; CHECK-LABEL: test_FMSUB_ASSOC_EXT4:
401; CHECK:       # %bb.0:
402; CHECK-NEXT:    fmuls 0, 3, 4
403; CHECK-NEXT:    fmadds 0, 1, 2, 0
404; CHECK-NEXT:    fsub 1, 5, 0
405; CHECK-NEXT:    blr
406;
407; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT4:
408; CHECK-VSX:       # %bb.0:
409; CHECK-VSX-NEXT:    fmuls 0, 3, 4
410; CHECK-VSX-NEXT:    fmadds 0, 1, 2, 0
411; CHECK-VSX-NEXT:    xssubdp 1, 5, 0
412; CHECK-VSX-NEXT:    blr
413;
414; CHECK-SPE-LABEL: test_FMSUB_ASSOC_EXT4:
415; CHECK-SPE:       # %bb.0:
416; CHECK-SPE-NEXT:    efsmul 3, 3, 4
417; CHECK-SPE-NEXT:    efsmul 4, 5, 6
418; CHECK-SPE-NEXT:    efsadd 3, 3, 4
419; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
420; CHECK-SPE-NEXT:    efdcfs 3, 3
421; CHECK-SPE-NEXT:    efdsub 4, 4, 3
422; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
423; CHECK-SPE-NEXT:    blr
424                                 float %D, double %E) {
425  %F = fmul float %A, %B          ; <float> [#uses=1]
426  %G = fmul float %C, %D          ; <float> [#uses=1]
427  %H = fadd float %F, %G          ; <float> [#uses=1]
428  %I = fpext float %H to double   ; <double> [#uses=1]
429  %J = fsub double %E, %I         ; <double> [#uses=1]
430  ret double %J
431}
432
433define double @test_reassoc_FMADD_ASSOC1(double %A, double %B, double %C,
434; CHECK-LABEL: test_reassoc_FMADD_ASSOC1:
435; CHECK:       # %bb.0:
436; CHECK-NEXT:    fmadd 0, 3, 4, 5
437; CHECK-NEXT:    fmadd 1, 1, 2, 0
438; CHECK-NEXT:    blr
439;
440; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC1:
441; CHECK-VSX:       # %bb.0:
442; CHECK-VSX-NEXT:    xsmaddmdp 3, 4, 5
443; CHECK-VSX-NEXT:    xsmaddadp 3, 1, 2
444; CHECK-VSX-NEXT:    fmr 1, 3
445; CHECK-VSX-NEXT:    blr
446;
447; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC1:
448; CHECK-SPE:       # %bb.0:
449; CHECK-SPE-NEXT:    evmergelo 9, 9, 10
450; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
451; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
452; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
453; CHECK-SPE-NEXT:    efdmul 4, 7, 9
454; CHECK-SPE-NEXT:    efdmul 3, 3, 5
455; CHECK-SPE-NEXT:    evldd 5, 8(1)
456; CHECK-SPE-NEXT:    efdadd 3, 3, 4
457; CHECK-SPE-NEXT:    efdadd 4, 3, 5
458; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
459; CHECK-SPE-NEXT:    blr
460                                 double %D, double %E) {
461  %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
462  %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
463  %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
464  %I = fadd reassoc double %H, %E         ; <double> [#uses=1]
465  ret double %I
466}
467
468define double @test_reassoc_FMADD_ASSOC2(double %A, double %B, double %C,
469; CHECK-LABEL: test_reassoc_FMADD_ASSOC2:
470; CHECK:       # %bb.0:
471; CHECK-NEXT:    fmadd 0, 3, 4, 5
472; CHECK-NEXT:    fmadd 1, 1, 2, 0
473; CHECK-NEXT:    blr
474;
475; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC2:
476; CHECK-VSX:       # %bb.0:
477; CHECK-VSX-NEXT:    xsmaddmdp 3, 4, 5
478; CHECK-VSX-NEXT:    xsmaddadp 3, 1, 2
479; CHECK-VSX-NEXT:    fmr 1, 3
480; CHECK-VSX-NEXT:    blr
481;
482; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC2:
483; CHECK-SPE:       # %bb.0:
484; CHECK-SPE-NEXT:    evmergelo 9, 9, 10
485; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
486; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
487; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
488; CHECK-SPE-NEXT:    efdmul 4, 7, 9
489; CHECK-SPE-NEXT:    efdmul 3, 3, 5
490; CHECK-SPE-NEXT:    evldd 5, 8(1)
491; CHECK-SPE-NEXT:    efdadd 3, 3, 4
492; CHECK-SPE-NEXT:    efdadd 4, 5, 3
493; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
494; CHECK-SPE-NEXT:    blr
495                                 double %D, double %E) {
496  %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
497  %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
498  %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
499  %I = fadd reassoc double %E, %H         ; <double> [#uses=1]
500  ret double %I
501}
502
503; FIXME: -ffp-contract=fast does NOT work here?
504define double @test_reassoc_FMSUB_ASSOC1(double %A, double %B, double %C,
505; CHECK-LABEL: test_reassoc_FMSUB_ASSOC1:
506; CHECK:       # %bb.0:
507; CHECK-NEXT:    fmul 0, 3, 4
508; CHECK-NEXT:    fmadd 0, 1, 2, 0
509; CHECK-NEXT:    fsub 1, 0, 5
510; CHECK-NEXT:    blr
511;
512; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC1:
513; CHECK-VSX:       # %bb.0:
514; CHECK-VSX-NEXT:    xsmuldp 0, 3, 4
515; CHECK-VSX-NEXT:    xsmaddadp 0, 1, 2
516; CHECK-VSX-NEXT:    xssubdp 1, 0, 5
517; CHECK-VSX-NEXT:    blr
518;
519; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC1:
520; CHECK-SPE:       # %bb.0:
521; CHECK-SPE-NEXT:    evmergelo 9, 9, 10
522; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
523; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
524; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
525; CHECK-SPE-NEXT:    efdmul 4, 7, 9
526; CHECK-SPE-NEXT:    efdmul 3, 3, 5
527; CHECK-SPE-NEXT:    evldd 5, 8(1)
528; CHECK-SPE-NEXT:    efdadd 3, 3, 4
529; CHECK-SPE-NEXT:    efdsub 4, 3, 5
530; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
531; CHECK-SPE-NEXT:    blr
532                                 double %D, double %E) {
533  %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
534  %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
535  %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
536  %I = fsub reassoc double %H, %E         ; <double> [#uses=1]
537  ret double %I
538}
539
540define double @test_reassoc_FMSUB_ASSOC11(double %A, double %B, double %C,
541; CHECK-LABEL: test_reassoc_FMSUB_ASSOC11:
542; CHECK:       # %bb.0:
543; CHECK-NEXT:    fmsub 0, 3, 4, 5
544; CHECK-NEXT:    fmadd 1, 1, 2, 0
545; CHECK-NEXT:    blr
546;
547; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC11:
548; CHECK-VSX:       # %bb.0:
549; CHECK-VSX-NEXT:    xsmsubmdp 3, 4, 5
550; CHECK-VSX-NEXT:    xsmaddadp 3, 1, 2
551; CHECK-VSX-NEXT:    fmr 1, 3
552; CHECK-VSX-NEXT:    blr
553;
554; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC11:
555; CHECK-SPE:       # %bb.0:
556; CHECK-SPE-NEXT:    evmergelo 9, 9, 10
557; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
558; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
559; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
560; CHECK-SPE-NEXT:    efdmul 4, 7, 9
561; CHECK-SPE-NEXT:    efdmul 3, 3, 5
562; CHECK-SPE-NEXT:    evldd 5, 8(1)
563; CHECK-SPE-NEXT:    efdadd 3, 3, 4
564; CHECK-SPE-NEXT:    efdsub 4, 3, 5
565; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
566; CHECK-SPE-NEXT:    blr
567                                 double %D, double %E) {
568  %F = fmul contract reassoc double %A, %B         ; <double> [#uses=1]
569  %G = fmul contract reassoc double %C, %D         ; <double> [#uses=1]
570  %H = fadd contract reassoc double %F, %G         ; <double> [#uses=1]
571  %I = fsub contract reassoc double %H, %E         ; <double> [#uses=1]
572  ret double %I
573}
574
575
576define double @test_reassoc_FMSUB_ASSOC2(double %A, double %B, double %C,
577; CHECK-LABEL: test_reassoc_FMSUB_ASSOC2:
578; CHECK:       # %bb.0:
579; CHECK-NEXT:    fmul 0, 3, 4
580; CHECK-NEXT:    fmadd 0, 1, 2, 0
581; CHECK-NEXT:    fsub 1, 5, 0
582; CHECK-NEXT:    blr
583;
584; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC2:
585; CHECK-VSX:       # %bb.0:
586; CHECK-VSX-NEXT:    xsmuldp 0, 3, 4
587; CHECK-VSX-NEXT:    xsmaddadp 0, 1, 2
588; CHECK-VSX-NEXT:    xssubdp 1, 5, 0
589; CHECK-VSX-NEXT:    blr
590;
591; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC2:
592; CHECK-SPE:       # %bb.0:
593; CHECK-SPE-NEXT:    evmergelo 9, 9, 10
594; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
595; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
596; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
597; CHECK-SPE-NEXT:    efdmul 4, 7, 9
598; CHECK-SPE-NEXT:    efdmul 3, 3, 5
599; CHECK-SPE-NEXT:    evldd 5, 8(1)
600; CHECK-SPE-NEXT:    efdadd 3, 3, 4
601; CHECK-SPE-NEXT:    efdsub 4, 5, 3
602; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
603; CHECK-SPE-NEXT:    blr
604                                 double %D, double %E) {
605  %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
606  %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
607  %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
608  %I = fsub reassoc double %E, %H         ; <double> [#uses=1]
609  ret double %I
610}
611
612define double @test_fast_FMSUB_ASSOC2(double %A, double %B, double %C,
613; CHECK-LABEL: test_fast_FMSUB_ASSOC2:
614; CHECK:       # %bb.0:
615; CHECK-NEXT:    fmul 0, 3, 4
616; CHECK-NEXT:    fmadd 0, 1, 2, 0
617; CHECK-NEXT:    fsub 1, 5, 0
618; CHECK-NEXT:    blr
619;
620; CHECK-VSX-LABEL: test_fast_FMSUB_ASSOC2:
621; CHECK-VSX:       # %bb.0:
622; CHECK-VSX-NEXT:    xsmuldp 0, 3, 4
623; CHECK-VSX-NEXT:    xsmaddadp 0, 1, 2
624; CHECK-VSX-NEXT:    xssubdp 1, 5, 0
625; CHECK-VSX-NEXT:    blr
626;
627; CHECK-SPE-LABEL: test_fast_FMSUB_ASSOC2:
628; CHECK-SPE:       # %bb.0:
629; CHECK-SPE-NEXT:    evmergelo 9, 9, 10
630; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
631; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
632; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
633; CHECK-SPE-NEXT:    efdmul 4, 7, 9
634; CHECK-SPE-NEXT:    efdmul 3, 3, 5
635; CHECK-SPE-NEXT:    evldd 5, 8(1)
636; CHECK-SPE-NEXT:    efdadd 3, 3, 4
637; CHECK-SPE-NEXT:    efdsub 4, 5, 3
638; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
639; CHECK-SPE-NEXT:    blr
640                                 double %D, double %E) {
641  %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
642  %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
643  %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
644  %I = fsub reassoc nsz double %E, %H         ; <double> [#uses=1]
645  ret double %I
646}
647
648define double @test_reassoc_FMADD_ASSOC_EXT1(float %A, float %B, double %C,
649; CHECK-LABEL: test_reassoc_FMADD_ASSOC_EXT1:
650; CHECK:       # %bb.0:
651; CHECK-NEXT:    fmadd 0, 1, 2, 5
652; CHECK-NEXT:    fmadd 1, 3, 4, 0
653; CHECK-NEXT:    blr
654;
655; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC_EXT1:
656; CHECK-VSX:       # %bb.0:
657; CHECK-VSX-NEXT:    xsmaddmdp 1, 2, 5
658; CHECK-VSX-NEXT:    xsmaddadp 1, 3, 4
659; CHECK-VSX-NEXT:    blr
660;
661; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC_EXT1:
662; CHECK-SPE:       # %bb.0:
663; CHECK-SPE-NEXT:    efsmul 3, 3, 4
664; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
665; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
666; CHECK-SPE-NEXT:    efdcfs 3, 3
667; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
668; CHECK-SPE-NEXT:    efdmul 5, 5, 7
669; CHECK-SPE-NEXT:    efdadd 3, 5, 3
670; CHECK-SPE-NEXT:    efdadd 4, 3, 4
671; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
672; CHECK-SPE-NEXT:    blr
673                                 double %D, double %E) {
674  %F = fmul reassoc float %A, %B         ; <float> [#uses=1]
675  %G = fpext float %F to double   ; <double> [#uses=1]
676  %H = fmul reassoc double %C, %D         ; <double> [#uses=1]
677  %I = fadd reassoc double %H, %G         ; <double> [#uses=1]
678  %J = fadd reassoc double %I, %E         ; <double> [#uses=1]
679  ret double %J
680}
681
682define double @test_reassoc_FMADD_ASSOC_EXT2(float %A, float %B, float %C,
683; CHECK-LABEL: test_reassoc_FMADD_ASSOC_EXT2:
684; CHECK:       # %bb.0:
685; CHECK-NEXT:    fmadd 0, 3, 4, 5
686; CHECK-NEXT:    fmadd 1, 1, 2, 0
687; CHECK-NEXT:    blr
688;
689; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC_EXT2:
690; CHECK-VSX:       # %bb.0:
691; CHECK-VSX-NEXT:    xsmaddmdp 3, 4, 5
692; CHECK-VSX-NEXT:    xsmaddadp 3, 1, 2
693; CHECK-VSX-NEXT:    fmr 1, 3
694; CHECK-VSX-NEXT:    blr
695;
696; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC_EXT2:
697; CHECK-SPE:       # %bb.0:
698; CHECK-SPE-NEXT:    efsmul 3, 3, 4
699; CHECK-SPE-NEXT:    efsmul 4, 5, 6
700; CHECK-SPE-NEXT:    efsadd 3, 3, 4
701; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
702; CHECK-SPE-NEXT:    efdcfs 3, 3
703; CHECK-SPE-NEXT:    efdadd 4, 3, 4
704; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
705; CHECK-SPE-NEXT:    blr
706                                 float %D, double %E) {
707  %F = fmul reassoc float %A, %B         ; <float> [#uses=1]
708  %G = fmul reassoc float %C, %D         ; <float> [#uses=1]
709  %H = fadd reassoc float %F, %G         ; <float> [#uses=1]
710  %I = fpext float %H to double   ; <double> [#uses=1]
711  %J = fadd reassoc double %I, %E         ; <double> [#uses=1]
712  ret double %J
713}
714
715define double @test_reassoc_FMADD_ASSOC_EXT3(float %A, float %B, double %C,
716; CHECK-LABEL: test_reassoc_FMADD_ASSOC_EXT3:
717; CHECK:       # %bb.0:
718; CHECK-NEXT:    fmadd 0, 1, 2, 5
719; CHECK-NEXT:    fmadd 1, 3, 4, 0
720; CHECK-NEXT:    blr
721;
722; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC_EXT3:
723; CHECK-VSX:       # %bb.0:
724; CHECK-VSX-NEXT:    xsmaddmdp 1, 2, 5
725; CHECK-VSX-NEXT:    xsmaddadp 1, 3, 4
726; CHECK-VSX-NEXT:    blr
727;
728; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC_EXT3:
729; CHECK-SPE:       # %bb.0:
730; CHECK-SPE-NEXT:    efsmul 3, 3, 4
731; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
732; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
733; CHECK-SPE-NEXT:    efdcfs 3, 3
734; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
735; CHECK-SPE-NEXT:    efdmul 5, 5, 7
736; CHECK-SPE-NEXT:    efdadd 3, 5, 3
737; CHECK-SPE-NEXT:    efdadd 4, 4, 3
738; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
739; CHECK-SPE-NEXT:    blr
740                                 double %D, double %E) {
741  %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
742  %G = fpext float %F to double   ; <double> [#uses=1]
743  %H = fmul reassoc double %C, %D         ; <double> [#uses=1]
744  %I = fadd reassoc double %H, %G         ; <double> [#uses=1]
745  %J = fadd reassoc double %E, %I         ; <double> [#uses=1]
746  ret double %J
747}
748
749define double @test_reassoc_FMADD_ASSOC_EXT4(float %A, float %B, float %C,
750; CHECK-LABEL: test_reassoc_FMADD_ASSOC_EXT4:
751; CHECK:       # %bb.0:
752; CHECK-NEXT:    fmadd 0, 3, 4, 5
753; CHECK-NEXT:    fmadd 1, 1, 2, 0
754; CHECK-NEXT:    blr
755;
756; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC_EXT4:
757; CHECK-VSX:       # %bb.0:
758; CHECK-VSX-NEXT:    xsmaddmdp 3, 4, 5
759; CHECK-VSX-NEXT:    xsmaddadp 3, 1, 2
760; CHECK-VSX-NEXT:    fmr 1, 3
761; CHECK-VSX-NEXT:    blr
762;
763; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC_EXT4:
764; CHECK-SPE:       # %bb.0:
765; CHECK-SPE-NEXT:    efsmul 3, 3, 4
766; CHECK-SPE-NEXT:    efsmul 4, 5, 6
767; CHECK-SPE-NEXT:    efsadd 3, 3, 4
768; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
769; CHECK-SPE-NEXT:    efdcfs 3, 3
770; CHECK-SPE-NEXT:    efdadd 4, 4, 3
771; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
772; CHECK-SPE-NEXT:    blr
773                                 float %D, double %E) {
774  %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
775  %G = fmul reassoc float %C, %D          ; <float> [#uses=1]
776  %H = fadd reassoc float %F, %G          ; <float> [#uses=1]
777  %I = fpext float %H to double   ; <double> [#uses=1]
778  %J = fadd reassoc double %E, %I         ; <double> [#uses=1]
779  ret double %J
780}
781
782define double @test_reassoc_FMSUB_ASSOC_EXT1(float %A, float %B, double %C,
783; CHECK-LABEL: test_reassoc_FMSUB_ASSOC_EXT1:
784; CHECK:       # %bb.0:
785; CHECK-NEXT:    fmsub 0, 1, 2, 5
786; CHECK-NEXT:    fmadd 1, 3, 4, 0
787; CHECK-NEXT:    blr
788;
789; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC_EXT1:
790; CHECK-VSX:       # %bb.0:
791; CHECK-VSX-NEXT:    xsmsubmdp 1, 2, 5
792; CHECK-VSX-NEXT:    xsmaddadp 1, 3, 4
793; CHECK-VSX-NEXT:    blr
794;
795; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC_EXT1:
796; CHECK-SPE:       # %bb.0:
797; CHECK-SPE-NEXT:    efsmul 3, 3, 4
798; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
799; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
800; CHECK-SPE-NEXT:    efdcfs 3, 3
801; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
802; CHECK-SPE-NEXT:    efdmul 5, 5, 7
803; CHECK-SPE-NEXT:    efdadd 3, 5, 3
804; CHECK-SPE-NEXT:    efdsub 4, 3, 4
805; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
806; CHECK-SPE-NEXT:    blr
807                                 double %D, double %E) {
808  %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
809  %G = fpext float %F to double   ; <double> [#uses=1]
810  %H = fmul reassoc double %C, %D         ; <double> [#uses=1]
811  %I = fadd reassoc double %H, %G         ; <double> [#uses=1]
812  %J = fsub reassoc double %I, %E         ; <double> [#uses=1]
813  ret double %J
814}
815
816define double @test_reassoc_FMSUB_ASSOC_EXT2(float %A, float %B, float %C,
817; CHECK-LABEL: test_reassoc_FMSUB_ASSOC_EXT2:
818; CHECK:       # %bb.0:
819; CHECK-NEXT:    fmsub 0, 3, 4, 5
820; CHECK-NEXT:    fmadd 1, 1, 2, 0
821; CHECK-NEXT:    blr
822;
823; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC_EXT2:
824; CHECK-VSX:       # %bb.0:
825; CHECK-VSX-NEXT:    xsmsubmdp 3, 4, 5
826; CHECK-VSX-NEXT:    xsmaddadp 3, 1, 2
827; CHECK-VSX-NEXT:    fmr 1, 3
828; CHECK-VSX-NEXT:    blr
829;
830; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC_EXT2:
831; CHECK-SPE:       # %bb.0:
832; CHECK-SPE-NEXT:    efsmul 3, 3, 4
833; CHECK-SPE-NEXT:    efsmul 4, 5, 6
834; CHECK-SPE-NEXT:    efsadd 3, 3, 4
835; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
836; CHECK-SPE-NEXT:    efdcfs 3, 3
837; CHECK-SPE-NEXT:    efdsub 4, 3, 4
838; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
839; CHECK-SPE-NEXT:    blr
840                                 float %D, double %E) {
841  %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
842  %G = fmul reassoc float %C, %D          ; <float> [#uses=1]
843  %H = fadd reassoc float %F, %G          ; <float> [#uses=1]
844  %I = fpext float %H to double   ; <double> [#uses=1]
845  %J = fsub reassoc double %I, %E         ; <double> [#uses=1]
846  ret double %J
847}
848
849define double @test_reassoc_FMSUB_ASSOC_EXT3(float %A, float %B, double %C,
850; CHECK-LABEL: test_reassoc_FMSUB_ASSOC_EXT3:
851; CHECK:       # %bb.0:
852; CHECK-NEXT:    fneg 0, 1
853; CHECK-NEXT:    fmadd 0, 0, 2, 5
854; CHECK-NEXT:    fneg 1, 3
855; CHECK-NEXT:    fmadd 1, 1, 4, 0
856; CHECK-NEXT:    blr
857;
858; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC_EXT3:
859; CHECK-VSX:       # %bb.0:
860; CHECK-VSX-NEXT:    xsnegdp 1, 1
861; CHECK-VSX-NEXT:    xsnegdp 0, 3
862; CHECK-VSX-NEXT:    xsmaddmdp 1, 2, 5
863; CHECK-VSX-NEXT:    xsmaddadp 1, 0, 4
864; CHECK-VSX-NEXT:    blr
865;
866; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC_EXT3:
867; CHECK-SPE:       # %bb.0:
868; CHECK-SPE-NEXT:    efsmul 3, 3, 4
869; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
870; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
871; CHECK-SPE-NEXT:    efdcfs 3, 3
872; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
873; CHECK-SPE-NEXT:    efdmul 5, 5, 7
874; CHECK-SPE-NEXT:    efdadd 3, 5, 3
875; CHECK-SPE-NEXT:    efdsub 4, 4, 3
876; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
877; CHECK-SPE-NEXT:    blr
878                                 double %D, double %E) {
879  %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
880  %G = fpext float %F to double   ; <double> [#uses=1]
881  %H = fmul reassoc double %C, %D         ; <double> [#uses=1]
882  %I = fadd reassoc double %H, %G         ; <double> [#uses=1]
883  %J = fsub reassoc double %E, %I         ; <double> [#uses=1]
884  ret double %J
885}
886
887; fnmsub/xsnmsubadp may affect the sign of zero, we need nsz flag
888; to ensure generating them
889define double @test_fast_FMSUB_ASSOC_EXT3(float %A, float %B, double %C,
890; CHECK-LABEL: test_fast_FMSUB_ASSOC_EXT3:
891; CHECK:       # %bb.0:
892; CHECK-NEXT:    fnmsub 0, 1, 2, 5
893; CHECK-NEXT:    fnmsub 1, 3, 4, 0
894; CHECK-NEXT:    blr
895;
896; CHECK-VSX-LABEL: test_fast_FMSUB_ASSOC_EXT3:
897; CHECK-VSX:       # %bb.0:
898; CHECK-VSX-NEXT:    xsnmsubmdp 1, 2, 5
899; CHECK-VSX-NEXT:    xsnmsubadp 1, 3, 4
900; CHECK-VSX-NEXT:    blr
901;
902; CHECK-SPE-LABEL: test_fast_FMSUB_ASSOC_EXT3:
903; CHECK-SPE:       # %bb.0:
904; CHECK-SPE-NEXT:    efsmul 3, 3, 4
905; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
906; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
907; CHECK-SPE-NEXT:    efdcfs 3, 3
908; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
909; CHECK-SPE-NEXT:    efdmul 5, 5, 7
910; CHECK-SPE-NEXT:    efdadd 3, 5, 3
911; CHECK-SPE-NEXT:    efdsub 4, 4, 3
912; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
913; CHECK-SPE-NEXT:    blr
914                                             double %D, double %E) {
915  %F = fmul reassoc float %A, %B
916  %G = fpext float %F to double
917  %H = fmul reassoc double %C, %D
918  %I = fadd reassoc nsz double %H, %G
919  %J = fsub reassoc nsz double %E, %I
920  ret double %J
921}
922
923define double @test_reassoc_FMSUB_ASSOC_EXT4(float %A, float %B, float %C,
924; CHECK-LABEL: test_reassoc_FMSUB_ASSOC_EXT4:
925; CHECK:       # %bb.0:
926; CHECK-NEXT:    fneg 0, 3
927; CHECK-NEXT:    fmadd 0, 0, 4, 5
928; CHECK-NEXT:    fneg 1, 1
929; CHECK-NEXT:    fmadd 1, 1, 2, 0
930; CHECK-NEXT:    blr
931;
932; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC_EXT4:
933; CHECK-VSX:       # %bb.0:
934; CHECK-VSX-NEXT:    xsnegdp 0, 3
935; CHECK-VSX-NEXT:    xsnegdp 1, 1
936; CHECK-VSX-NEXT:    xsmaddmdp 0, 4, 5
937; CHECK-VSX-NEXT:    xsmaddadp 0, 1, 2
938; CHECK-VSX-NEXT:    fmr 1, 0
939; CHECK-VSX-NEXT:    blr
940;
941; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC_EXT4:
942; CHECK-SPE:       # %bb.0:
943; CHECK-SPE-NEXT:    efsmul 3, 3, 4
944; CHECK-SPE-NEXT:    efsmul 4, 5, 6
945; CHECK-SPE-NEXT:    efsadd 3, 3, 4
946; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
947; CHECK-SPE-NEXT:    efdcfs 3, 3
948; CHECK-SPE-NEXT:    efdsub 4, 4, 3
949; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
950; CHECK-SPE-NEXT:    blr
951                                 float %D, double %E) {
952  %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
953  %G = fmul reassoc float %C, %D          ; <float> [#uses=1]
954  %H = fadd reassoc float %F, %G          ; <float> [#uses=1]
955  %I = fpext float %H to double   ; <double> [#uses=1]
956  %J = fsub reassoc double %E, %I         ; <double> [#uses=1]
957  ret double %J
958}
959
960define double @test_fast_FMSUB_ASSOC_EXT4(float %A, float %B, float %C,
961; CHECK-LABEL: test_fast_FMSUB_ASSOC_EXT4:
962; CHECK:       # %bb.0:
963; CHECK-NEXT:    fnmsub 0, 3, 4, 5
964; CHECK-NEXT:    fnmsub 1, 1, 2, 0
965; CHECK-NEXT:    blr
966;
967; CHECK-VSX-LABEL: test_fast_FMSUB_ASSOC_EXT4:
968; CHECK-VSX:       # %bb.0:
969; CHECK-VSX-NEXT:    xsnmsubmdp 3, 4, 5
970; CHECK-VSX-NEXT:    xsnmsubadp 3, 1, 2
971; CHECK-VSX-NEXT:    fmr 1, 3
972; CHECK-VSX-NEXT:    blr
973;
974; CHECK-SPE-LABEL: test_fast_FMSUB_ASSOC_EXT4:
975; CHECK-SPE:       # %bb.0:
976; CHECK-SPE-NEXT:    efsmul 3, 3, 4
977; CHECK-SPE-NEXT:    efsmul 4, 5, 6
978; CHECK-SPE-NEXT:    efsadd 3, 3, 4
979; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
980; CHECK-SPE-NEXT:    efdcfs 3, 3
981; CHECK-SPE-NEXT:    efdsub 4, 4, 3
982; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
983; CHECK-SPE-NEXT:    blr
984                                          float %D, double %E) {
985  %F = fmul reassoc float %A, %B
986  %G = fmul reassoc float %C, %D
987  %H = fadd reassoc nsz float %F, %G
988  %I = fpext float %H to double
989  %J = fsub reassoc nsz double %E, %I
990  ret double %J
991}
992