1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" 3target triple = "powerpc64-unknown-linux-gnu" 4; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -mattr=-isel < %s | FileCheck %s --implicit-check-not isel 5 6define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) { 7; CHECK-LABEL: testExpandISELToIfElse: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: cmpwi r3, 0 10; CHECK-NEXT: ble cr0, .LBB0_2 11; CHECK-NEXT: # %bb.1: 12; CHECK-NEXT: addi r4, r3, 1 13; CHECK-NEXT: .LBB0_2: # %entry 14; CHECK-NEXT: extsw r3, r4 15; CHECK-NEXT: blr 16entry: 17 %cmp = icmp sgt i32 %i, 0 18 %add = add nsw i32 %i, 1 19 %cond = select i1 %cmp, i32 %add, i32 %j 20 ret i32 %cond 21 22} 23 24define signext i32 @testExpandISELToIf(i32 signext %i, i32 signext %j) { 25; CHECK-LABEL: testExpandISELToIf: 26; CHECK: # %bb.0: # %entry 27; CHECK-NEXT: cmpwi r3, 0 28; CHECK-NEXT: bgt cr0, .LBB1_2 29; CHECK-NEXT: # %bb.1: # %entry 30; CHECK-NEXT: mr r4, r3 31; CHECK-NEXT: .LBB1_2: # %entry 32; CHECK-NEXT: mr r3, r4 33; CHECK-NEXT: blr 34entry: 35 %cmp = icmp sgt i32 %i, 0 36 %cond = select i1 %cmp, i32 %j, i32 %i 37 ret i32 %cond 38 39} 40 41define signext i32 @testExpandISELToElse(i32 signext %i, i32 signext %j) { 42; CHECK-LABEL: testExpandISELToElse: 43; CHECK: # %bb.0: # %entry 44; CHECK-NEXT: cmpwi r3, 0 45; CHECK-NEXT: bgtlr cr0 46; CHECK-NEXT: # %bb.1: # %entry 47; CHECK-NEXT: mr r3, r4 48; CHECK-NEXT: blr 49entry: 50 %cmp = icmp sgt i32 %i, 0 51 %cond = select i1 %cmp, i32 %i, i32 %j 52 ret i32 %cond 53 54} 55 56define signext i32 @testExpandISELToNull(i32 signext %i, i32 signext %j) { 57; CHECK-LABEL: testExpandISELToNull: 58; CHECK: # %bb.0: # %entry 59; CHECK-NEXT: blr 60entry: 61 %cmp = icmp sgt i32 %i, 0 62 %cond = select i1 %cmp, i32 %i, i32 %i 63 ret i32 %cond 64 65} 66 67define signext i32 @testExpandISELsTo2ORIs2ADDIs(i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { 68; CHECK-LABEL: testExpandISELsTo2ORIs2ADDIs: 69; CHECK: # %bb.0: # %entry 70; CHECK-NEXT: cmpwi r7, 0 71; CHECK-NEXT: bgt cr0, .LBB4_2 72; CHECK-NEXT: # %bb.1: # %entry 73; CHECK-NEXT: mr r7, r4 74; CHECK-NEXT: .LBB4_2: # %entry 75; CHECK-NEXT: bgt cr0, .LBB4_4 76; CHECK-NEXT: # %bb.3: # %entry 77; CHECK-NEXT: mr r5, r6 78; CHECK-NEXT: .LBB4_4: # %entry 79; CHECK-NEXT: add r3, r7, r5 80; CHECK-NEXT: extsw r3, r3 81; CHECK-NEXT: blr 82entry: 83 %cmp = icmp sgt i32 %g, 0 84 %a.b = select i1 %cmp, i32 %g, i32 %b 85 %d.f = select i1 %cmp, i32 %d, i32 %f 86 %add = add nsw i32 %a.b, %d.f 87 ret i32 %add 88} 89 90define signext i32 @testExpandISELsTo2ORIs1ADDI(i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { 91; CHECK-LABEL: testExpandISELsTo2ORIs1ADDI: 92; CHECK: # %bb.0: # %entry 93; CHECK-NEXT: cmpwi r7, 0 94; CHECK-NEXT: bgt cr0, .LBB5_2 95; CHECK-NEXT: # %bb.1: # %entry 96; CHECK-NEXT: mr r3, r4 97; CHECK-NEXT: .LBB5_2: # %entry 98; CHECK-NEXT: bgt cr0, .LBB5_4 99; CHECK-NEXT: # %bb.3: # %entry 100; CHECK-NEXT: mr r5, r6 101; CHECK-NEXT: .LBB5_4: # %entry 102; CHECK-NEXT: add r3, r3, r5 103; CHECK-NEXT: extsw r3, r3 104; CHECK-NEXT: blr 105entry: 106 %cmp = icmp sgt i32 %g, 0 107 %a.b = select i1 %cmp, i32 %a, i32 %b 108 %d.f = select i1 %cmp, i32 %d, i32 %f 109 %add = add nsw i32 %a.b, %d.f 110 ret i32 %add 111} 112 113define signext i32 @testExpandISELsTo1ORI1ADDI(i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { 114; CHECK-LABEL: testExpandISELsTo1ORI1ADDI: 115; CHECK: # %bb.0: # %entry 116; CHECK-NEXT: cmpwi r7, 0 117; CHECK-NEXT: mr r7, r3 118; CHECK-NEXT: bgt cr0, .LBB6_2 119; CHECK-NEXT: # %bb.1: # %entry 120; CHECK-NEXT: mr r7, r4 121; CHECK-NEXT: .LBB6_2: # %entry 122; CHECK-NEXT: bgt cr0, .LBB6_4 123; CHECK-NEXT: # %bb.3: # %entry 124; CHECK-NEXT: mr r5, r6 125; CHECK-NEXT: .LBB6_4: # %entry 126; CHECK-NEXT: add r4, r7, r5 127; CHECK-NEXT: add r3, r3, r4 128; CHECK-NEXT: extsw r3, r3 129; CHECK-NEXT: blr 130entry: 131 %cmp = icmp sgt i32 %g, 0 132 %a.b = select i1 %cmp, i32 %a, i32 %b 133 %d.f = select i1 %cmp, i32 %d, i32 %f 134 %add1 = add nsw i32 %a.b, %d.f 135 %add2 = add nsw i32 %a, %add1 136 ret i32 %add2 137} 138 139define signext i32 @testExpandISELsTo0ORI2ADDIs(i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { 140; CHECK-LABEL: testExpandISELsTo0ORI2ADDIs: 141; CHECK: # %bb.0: # %entry 142; CHECK-NEXT: cmpwi r7, 0 143; CHECK-NEXT: mr r7, r3 144; CHECK-NEXT: bgt cr0, .LBB7_2 145; CHECK-NEXT: # %bb.1: # %entry 146; CHECK-NEXT: mr r7, r4 147; CHECK-NEXT: .LBB7_2: # %entry 148; CHECK-NEXT: mr r4, r5 149; CHECK-NEXT: bgt cr0, .LBB7_4 150; CHECK-NEXT: # %bb.3: # %entry 151; CHECK-NEXT: mr r4, r6 152; CHECK-NEXT: .LBB7_4: # %entry 153; CHECK-NEXT: add r4, r7, r4 154; CHECK-NEXT: add r3, r3, r4 155; CHECK-NEXT: sub r3, r3, r5 156; CHECK-NEXT: extsw r3, r3 157; CHECK-NEXT: blr 158entry: 159 %cmp = icmp sgt i32 %g, 0 160 %a.b = select i1 %cmp, i32 %a, i32 %b 161 %d.f = select i1 %cmp, i32 %d, i32 %f 162 %add1 = add nsw i32 %a.b, %d.f 163 %add2 = add nsw i32 %a, %add1 164 %sub1 = sub nsw i32 %add2, %d 165 ret i32 %sub1 166} 167 168@b = local_unnamed_addr global i32 0, align 4 169@a = local_unnamed_addr global i32 0, align 4 170; Function Attrs: norecurse nounwind readonly 171define signext i32 @testComplexISEL() #0 { 172; CHECK-LABEL: testComplexISEL: 173; CHECK: # %bb.0: # %entry 174; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 175; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 176; CHECK-NEXT: lwz r4, 0(r3) 177; CHECK-NEXT: li r3, 1 178; CHECK-NEXT: cmplwi r4, 0 179; CHECK-NEXT: bnelr cr0 180; CHECK-NEXT: # %bb.1: # %if.end 181; CHECK-NEXT: addis r3, r2, .LC1@toc@ha 182; CHECK-NEXT: addis r4, r2, .LC2@toc@ha 183; CHECK-NEXT: ld r3, .LC1@toc@l(r3) 184; CHECK-NEXT: ld r4, .LC2@toc@l(r4) 185; CHECK-NEXT: lwa r3, 0(r3) 186; CHECK-NEXT: xor r3, r3, r4 187; CHECK-NEXT: cntlzd r3, r3 188; CHECK-NEXT: rldicl r3, r3, 58, 63 189; CHECK-NEXT: blr 190entry: 191 %0 = load i32, ptr @b, align 4, !tbaa !1 192 %tobool = icmp eq i32 %0, 0 193 br i1 %tobool, label %if.end, label %cleanup 194 195if.end: 196 %1 = load i32, ptr @a, align 4, !tbaa !1 197 %conv = sext i32 %1 to i64 198 %2 = inttoptr i64 %conv to ptr 199 %cmp = icmp eq ptr %2, @testComplexISEL 200 %conv3 = zext i1 %cmp to i32 201 br label %cleanup 202 203cleanup: 204 %retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ] 205 ret i32 %retval.0 206 207} 208 209!1 = !{!2, !2, i64 0} 210!2 = !{!"int", !3, i64 0} 211!3 = !{!"omnipotent char", !4, i64 0} 212!4 = !{!"Simple C/C++ TBAA"} 213