xref: /llvm-project/llvm/test/CodeGen/PowerPC/expand-isel-to-branch.ll (revision d1924f0474b65fe3189ffd658a12f452e4696c28)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix < %s | FileCheck %s
3
4define noundef signext i32 @ham(ptr nocapture noundef %arg) #0 {
5; CHECK-LABEL: ham:
6; CHECK:       # %bb.0: # %bb
7; CHECK-NEXT:    lwz 4, 0(3)
8; CHECK-NEXT:    cmpwi 4, 750
9; CHECK-NEXT:    blt 0, L..BB0_2
10; CHECK-NEXT:  # %bb.1: # %bb
11; CHECK-NEXT:    li 4, 1
12; CHECK-NEXT:    b L..BB0_3
13; CHECK-NEXT:  L..BB0_2:
14; CHECK-NEXT:    addi 4, 4, 1
15; CHECK-NEXT:  L..BB0_3: # %bb
16; CHECK-NEXT:    stw 4, 0(3)
17; CHECK-NEXT:    li 3, 0
18; CHECK-NEXT:    blr
19bb:
20  %load = load i32, ptr %arg, align 4
21  %icmp = icmp slt i32 %load, 750
22  %add = add nsw i32 %load, 1
23  %select = select i1 %icmp, i32 %add, i32 1
24  store i32 %select, ptr %arg, align 4
25  ret i32 0
26}
27
28attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr8" "target-features"="+altivec,+bpermd,+crbits,+crypto,+direct-move,+extdiv,+htm,+isa-v206-instructions,+isa-v207-instructions,+power8-vector,+quadword-atomics,+vsx,-aix-small-local-exec-tls,-isa-v30-instructions,-isel,-power9-vector,-privileged,-rop-protect,-spe" }
29