xref: /llvm-project/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll (revision 8e901c255df45e38cb1d69a576804029e20868bf)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2target datalayout = "e-m:e-i64:64-n32:64"
3target triple = "powerpc64le-unknown-linux-gnu"
4; This file mainly tests the case that the two input registers of the ISEL instruction are the same register.
5; The foldable ISEL in this test case is introduced at register coalescing stage.
6
7; Before that stage we have:
8; %vreg18<def> = ISEL8 %vreg5, %vreg2, %vreg15<undef>;
9
10; At register coalescing stage, the register coalescer figures out it could remove the copy
11; from %vreg2 to %vreg5, put the original value %X3 into %vreg5 directly
12;  erased: 336r    %vreg5<def> = COPY %vreg2
13;  updated: 288B   %vreg5<def> = COPY %X3;
14
15; After that we have:
16;   updated: 416B   %vreg18<def> = ISEL8 %vreg5, %vreg5, %vreg15<undef>;
17
18; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -mattr=+isel < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE
19; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -mattr=-isel < %s | FileCheck %s --implicit-check-not isel
20%"struct.pov::ot_block_struct" = type { ptr, [3 x double], [3 x double], float, float, float, float, float, float, float, float, float, [3 x float], float, float, [3 x double], i16 }
21%"struct.pov::ot_node_struct" = type { %"struct.pov::ot_id_struct", ptr, [8 x ptr] }
22%"struct.pov::ot_id_struct" = type { i32, i32, i32, i32 }
23
24define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE(ptr %new_block) {
25; CHECK-GEN-ISEL-TRUE-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE:
26; CHECK-GEN-ISEL-TRUE:       # %bb.0: # %entry
27; CHECK-GEN-ISEL-TRUE-NEXT:    mflr r0
28; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_def_cfa_offset 64
29; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_offset lr, 16
30; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_offset r29, -24
31; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_offset r30, -16
32; CHECK-GEN-ISEL-TRUE-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
33; CHECK-GEN-ISEL-TRUE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
34; CHECK-GEN-ISEL-TRUE-NEXT:    stdu r1, -64(r1)
35; CHECK-GEN-ISEL-TRUE-NEXT:    mr r30, r3
36; CHECK-GEN-ISEL-TRUE-NEXT:    std r0, 80(r1)
37; CHECK-GEN-ISEL-TRUE-NEXT:    # implicit-def: $x3
38; CHECK-GEN-ISEL-TRUE-NEXT:    # implicit-def: $r29
39; CHECK-GEN-ISEL-TRUE-NEXT:    b .LBB0_2
40; CHECK-GEN-ISEL-TRUE-NEXT:    .p2align 4
41; CHECK-GEN-ISEL-TRUE-NEXT:  .LBB0_1: # %cond.false21.i156
42; CHECK-GEN-ISEL-TRUE-NEXT:    #
43; CHECK-GEN-ISEL-TRUE-NEXT:    addi r4, r29, 1
44; CHECK-GEN-ISEL-TRUE-NEXT:    srawi r4, r4, 1
45; CHECK-GEN-ISEL-TRUE-NEXT:    addze r29, r4
46; CHECK-GEN-ISEL-TRUE-NEXT:  .LBB0_2: # %while.cond11
47; CHECK-GEN-ISEL-TRUE-NEXT:    #
48; CHECK-GEN-ISEL-TRUE-NEXT:    lwz r4, 0(r3)
49; CHECK-GEN-ISEL-TRUE-NEXT:    cmplwi r4, 0
50; CHECK-GEN-ISEL-TRUE-NEXT:    beq cr0, .LBB0_5
51; CHECK-GEN-ISEL-TRUE-NEXT:  # %bb.3: # %while.body21
52; CHECK-GEN-ISEL-TRUE-NEXT:    #
53; CHECK-GEN-ISEL-TRUE-NEXT:    bl ZN3pov10pov_callocEmmPKciS1_pov
54; CHECK-GEN-ISEL-TRUE-NEXT:    nop
55; CHECK-GEN-ISEL-TRUE-NEXT:    std r3, 0(r3)
56; CHECK-GEN-ISEL-TRUE-NEXT:    bc 12, 4*cr5+lt, .LBB0_1
57; CHECK-GEN-ISEL-TRUE-NEXT:  # %bb.4: # %cond.true18.i153
58; CHECK-GEN-ISEL-TRUE-NEXT:    #
59; CHECK-GEN-ISEL-TRUE-NEXT:    srwi r29, r29, 1
60; CHECK-GEN-ISEL-TRUE-NEXT:    b .LBB0_2
61; CHECK-GEN-ISEL-TRUE-NEXT:  .LBB0_5: # %lor.rhs
62; CHECK-GEN-ISEL-TRUE-NEXT:    std r30, 16(r3)
63; CHECK-GEN-ISEL-TRUE-NEXT:    addi r1, r1, 64
64; CHECK-GEN-ISEL-TRUE-NEXT:    ld r0, 16(r1)
65; CHECK-GEN-ISEL-TRUE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
66; CHECK-GEN-ISEL-TRUE-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
67; CHECK-GEN-ISEL-TRUE-NEXT:    mtlr r0
68; CHECK-GEN-ISEL-TRUE-NEXT:    blr
69;
70; CHECK-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE:
71; CHECK:       # %bb.0: # %entry
72; CHECK-NEXT:    mflr r0
73; CHECK-NEXT:    .cfi_def_cfa_offset 64
74; CHECK-NEXT:    .cfi_offset lr, 16
75; CHECK-NEXT:    .cfi_offset r29, -24
76; CHECK-NEXT:    .cfi_offset r30, -16
77; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
78; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
79; CHECK-NEXT:    stdu r1, -64(r1)
80; CHECK-NEXT:    mr r30, r3
81; CHECK-NEXT:    std r0, 80(r1)
82; CHECK-NEXT:    # implicit-def: $x3
83; CHECK-NEXT:    # implicit-def: $r29
84; CHECK-NEXT:    b .LBB0_2
85; CHECK-NEXT:    .p2align 4
86; CHECK-NEXT:  .LBB0_1: # %cond.false21.i156
87; CHECK-NEXT:    #
88; CHECK-NEXT:    addi r4, r29, 1
89; CHECK-NEXT:    srawi r4, r4, 1
90; CHECK-NEXT:    addze r29, r4
91; CHECK-NEXT:  .LBB0_2: # %while.cond11
92; CHECK-NEXT:    #
93; CHECK-NEXT:    lwz r4, 0(r3)
94; CHECK-NEXT:    cmplwi r4, 0
95; CHECK-NEXT:    beq cr0, .LBB0_5
96; CHECK-NEXT:  # %bb.3: # %while.body21
97; CHECK-NEXT:    #
98; CHECK-NEXT:    bl ZN3pov10pov_callocEmmPKciS1_pov
99; CHECK-NEXT:    nop
100; CHECK-NEXT:    std r3, 0(r3)
101; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_1
102; CHECK-NEXT:  # %bb.4: # %cond.true18.i153
103; CHECK-NEXT:    #
104; CHECK-NEXT:    srwi r29, r29, 1
105; CHECK-NEXT:    b .LBB0_2
106; CHECK-NEXT:  .LBB0_5: # %lor.rhs
107; CHECK-NEXT:    std r30, 16(r3)
108; CHECK-NEXT:    addi r1, r1, 64
109; CHECK-NEXT:    ld r0, 16(r1)
110; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
111; CHECK-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
112; CHECK-NEXT:    mtlr r0
113; CHECK-NEXT:    blr
114entry:
115  br label %while.cond11
116
117while.cond11:
118  %this_node.0250 = phi ptr [ undef, %entry ], [ %1, %cond.false21.i156 ], [ %1, %cond.true18.i153 ]
119  %temp_id.sroa.21.1 = phi i32 [ undef, %entry ], [ %shr2039.i152, %cond.true18.i153 ], [ %div24.i155, %cond.false21.i156 ]
120  %0 = load i32, ptr undef, align 4
121  %cmp17 = icmp eq i32 0, %0
122  br i1 %cmp17, label %lor.rhs, label %while.body21
123
124lor.rhs:
125  %Values = getelementptr inbounds %"struct.pov::ot_node_struct", ptr %this_node.0250, i64 0, i32 1
126  store ptr %new_block, ptr %Values, align 8
127  ret void
128
129while.body21:
130  %call.i84 = tail call ptr @ZN3pov10pov_callocEmmPKciS1_pov()
131  store ptr %call.i84, ptr undef, align 8
132  %1 = bitcast ptr %call.i84 to ptr
133  br i1 undef, label %cond.true18.i153, label %cond.false21.i156
134
135cond.true18.i153:
136  %shr2039.i152 = lshr i32 %temp_id.sroa.21.1, 1
137  br label %while.cond11
138
139cond.false21.i156:
140  %add23.i154 = add nsw i32 %temp_id.sroa.21.1, 1
141  %div24.i155 = sdiv i32 %add23.i154, 2
142  br label %while.cond11
143}
144
145declare ptr @ZN3pov10pov_callocEmmPKciS1_pov()
146