xref: /llvm-project/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll (revision 427fb35192f1f7bb694a5910b05abc5925a798b2)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
5; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s \
6; RUN:   --check-prefix=CHECK-BE
7
8; This test checks that LSR properly recognizes lxvp/stxvp as load/store
9; intrinsics to avoid generating x-form instructions instead of d-forms.
10
11declare <256 x i1> @llvm.ppc.vsx.lxvp(ptr)
12declare void @llvm.ppc.vsx.stxvp(<256 x i1>, ptr)
13define void @foo(i32 zeroext %n, ptr %ptr, ptr %ptr2) {
14; CHECK-LABEL: foo:
15; CHECK:       # %bb.0: # %entry
16; CHECK-NEXT:    cmplwi r3, 0
17; CHECK-NEXT:    beqlr cr0
18; CHECK-NEXT:  # %bb.1: # %for.body.lr.ph
19; CHECK-NEXT:    addi r4, r4, 64
20; CHECK-NEXT:    addi r5, r5, 64
21; CHECK-NEXT:    mtctr r3
22; CHECK-NEXT:    .p2align 4
23; CHECK-NEXT:  .LBB0_2: # %for.body
24; CHECK-NEXT:    #
25; CHECK-NEXT:    lxvp vsp34, -64(r4)
26; CHECK-NEXT:    lxvp vsp36, -32(r4)
27; CHECK-NEXT:    lxvp vsp32, 0(r4)
28; CHECK-NEXT:    lxvp vsp38, 32(r4)
29; CHECK-NEXT:    addi r4, r4, 1
30; CHECK-NEXT:    stxvp vsp34, -64(r5)
31; CHECK-NEXT:    stxvp vsp36, -32(r5)
32; CHECK-NEXT:    stxvp vsp32, 0(r5)
33; CHECK-NEXT:    stxvp vsp38, 32(r5)
34; CHECK-NEXT:    addi r5, r5, 1
35; CHECK-NEXT:    bdnz .LBB0_2
36; CHECK-NEXT:  # %bb.3: # %for.cond.cleanup
37; CHECK-NEXT:    blr
38;
39; CHECK-BE-LABEL: foo:
40; CHECK-BE:       # %bb.0: # %entry
41; CHECK-BE-NEXT:    cmplwi r3, 0
42; CHECK-BE-NEXT:    beqlr cr0
43; CHECK-BE-NEXT:  # %bb.1: # %for.body.lr.ph
44; CHECK-BE-NEXT:    addi r4, r4, 64
45; CHECK-BE-NEXT:    addi r5, r5, 64
46; CHECK-BE-NEXT:    mtctr r3
47; CHECK-BE-NEXT:    .p2align 4
48; CHECK-BE-NEXT:  .LBB0_2: # %for.body
49; CHECK-BE-NEXT:    #
50; CHECK-BE-NEXT:    lxvp vsp34, -64(r4)
51; CHECK-BE-NEXT:    lxvp vsp36, -32(r4)
52; CHECK-BE-NEXT:    lxvp vsp32, 0(r4)
53; CHECK-BE-NEXT:    lxvp vsp38, 32(r4)
54; CHECK-BE-NEXT:    addi r4, r4, 1
55; CHECK-BE-NEXT:    stxvp vsp34, -64(r5)
56; CHECK-BE-NEXT:    stxvp vsp36, -32(r5)
57; CHECK-BE-NEXT:    stxvp vsp32, 0(r5)
58; CHECK-BE-NEXT:    stxvp vsp38, 32(r5)
59; CHECK-BE-NEXT:    addi r5, r5, 1
60; CHECK-BE-NEXT:    bdnz .LBB0_2
61; CHECK-BE-NEXT:  # %bb.3: # %for.cond.cleanup
62; CHECK-BE-NEXT:    blr
63entry:
64  %cmp35.not = icmp eq i32 %n, 0
65  br i1 %cmp35.not, label %for.cond.cleanup, label %for.body.lr.ph
66
67for.body.lr.ph:
68  %wide.trip.count = zext i32 %n to i64
69  br label %for.body
70
71for.cond.cleanup:
72  ret void
73
74for.body:
75  %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
76  %0 = getelementptr i8, ptr %ptr, i64 %indvars.iv
77  %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %0)
78  %add2 = add nuw nsw i64 %indvars.iv, 32
79  %2 = getelementptr i8, ptr %ptr, i64 %add2
80  %3 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %2)
81  %add4 = add nuw nsw i64 %indvars.iv, 64
82  %4 = getelementptr i8, ptr %ptr, i64 %add4
83  %5 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %4)
84  %add6 = add nuw nsw i64 %indvars.iv, 96
85  %6 = getelementptr i8, ptr %ptr, i64 %add6
86  %7 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %6)
87  %8 = getelementptr i8, ptr %ptr2, i64 %indvars.iv
88  tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, ptr %8)
89  %9 = getelementptr i8, ptr %ptr2, i64 %add2
90  tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %3, ptr %9)
91  %10 = getelementptr i8, ptr %ptr2, i64 %add4
92  tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %5, ptr %10)
93  %11 = getelementptr i8, ptr %ptr2, i64 %add6
94  tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %7, ptr %11)
95  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
96  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
97  br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
98}
99
100