xref: /llvm-project/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir (revision 48904e9452de81375bd55d830d08e51cc8f2ec7e) 
1# RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu -start-after \
2# RUN:   ppc-mi-peepholes -ppc-late-peephole %s -o - | FileCheck %s
3
4---
5name:            testLXSSPX
6alignment:       16
7exposesReturnsTwice: false
8legalized:       false
9regBankSelected: false
10selected:        false
11tracksRegLiveness: true
12registers:
13  - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
14  - { id: 1, class: g8rc, preferred-register: '' }
15  - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
16  - { id: 3, class: gprc, preferred-register: '' }
17  - { id: 4, class: g8rc, preferred-register: '' }
18  - { id: 5, class: g8rc, preferred-register: '' }
19  - { id: 6, class: g8rc, preferred-register: '' }
20  - { id: 7, class: vssrc, preferred-register: '' }
21  - { id: 8, class: gprc, preferred-register: '' }
22  - { id: 9, class: g8rc, preferred-register: '' }
23  - { id: 10, class: g8rc, preferred-register: '' }
24  - { id: 11, class: g8rc, preferred-register: '' }
25  - { id: 12, class: vssrc, preferred-register: '' }
26  - { id: 13, class: vssrc, preferred-register: '' }
27liveins:
28  - { reg: '$x3', virtual-reg: '%0' }
29  - { reg: '$x4', virtual-reg: '%1' }
30body:             |
31  bb.0.entry:
32    liveins: $x3, $x4
33
34    %1 = COPY $x4
35    %0 = COPY $x3
36    %2 = COPY %1.sub_32
37    %3 = ADDI %2, 1
38    %5 = IMPLICIT_DEF
39    %4 = INSERT_SUBREG %5, killed %3, 1
40    %6 = LI8 97
41    %7 = LXSSPX %0, killed %6, implicit $rm
42    ; CHECK:  lfs [[REG1:[0-9]+]], 97(3)
43    %8 = ADDI %2, 2
44    %10 = IMPLICIT_DEF
45    %9 = INSERT_SUBREG %10, killed %8, 1
46    %11 = LI8 -92
47    %12 = LXSSPX %0, killed %11, implicit $rm
48    ; CHECK-NEXT:  lfs [[REG2:[0-9]+]], -92(3)
49    %13 = XSADDSP killed %7, killed %12
50    ; CHECK-NEXT:  xsaddsp {{[0-9]+}}, [[REG1]], [[REG2]]
51    $f1 = COPY %13
52    BLR8 implicit $lr8, implicit $rm, implicit $f1
53...
54
55
56---
57name:            testLXSDX
58tracksRegLiveness: true
59registers:
60  - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
61  - { id: 1, class: g8rc, preferred-register: '' }
62  - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
63  - { id: 3, class: gprc, preferred-register: '' }
64  - { id: 4, class: g8rc, preferred-register: '' }
65  - { id: 5, class: g8rc, preferred-register: '' }
66  - { id: 6, class: g8rc, preferred-register: '' }
67  - { id: 7, class: vsfrc, preferred-register: '' }
68  - { id: 8, class: gprc, preferred-register: '' }
69  - { id: 9, class: g8rc, preferred-register: '' }
70  - { id: 10, class: g8rc, preferred-register: '' }
71  - { id: 11, class: g8rc, preferred-register: '' }
72  - { id: 12, class: vsfrc, preferred-register: '' }
73  - { id: 13, class: vsfrc, preferred-register: '' }
74liveins:
75  - { reg: '$x3', virtual-reg: '%0' }
76  - { reg: '$x4', virtual-reg: '%1' }
77body:             |
78  bb.0.entry:
79    liveins: $x3, $x4
80
81    %1 = COPY $x4
82    %0 = COPY $x3
83    %2 = COPY %1.sub_32
84    %3 = ADDI %2, 1
85    %5 = IMPLICIT_DEF
86    %4 = INSERT_SUBREG %5, killed %3, 1
87    %6 = LI8 99
88    %7 = LXSDX %0, killed %6, implicit $rm
89    ; CHECK:  lfd [[REG1:[0-9]+]], 99(3)
90    %8 = ADDI %2, 2
91    %10 = IMPLICIT_DEF
92    %9 = INSERT_SUBREG %10, killed %8, 1
93    %11 = LI8 -120
94    %12 = LXSDX %0, killed %11, implicit $rm
95    ; CHECK-NEXT:  lfd [[REG2:[0-9]+]], -120(3)
96    %13 = XSADDDP killed %7, killed %12, implicit $rm
97    ; CHECK-NEXT:  xsadddp {{[0-9]+}}, [[REG1]], [[REG2]]
98    $f1 = COPY %13
99    BLR8 implicit $lr8, implicit $rm, implicit $f1
100...
101
102
103---
104name:            testSTXSSPX
105alignment:       16
106exposesReturnsTwice: false
107legalized:       false
108regBankSelected: false
109selected:        false
110tracksRegLiveness: true
111registers:
112  - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
113  - { id: 1, class: vssrc, preferred-register: '' }
114  - { id: 2, class: g8rc, preferred-register: '' }
115  - { id: 3, class: g8rc, preferred-register: '' }
116liveins:
117  - { reg: '$x3', virtual-reg: '%0' }
118  - { reg: '$f1', virtual-reg: '%1' }
119  - { reg: '$x5', virtual-reg: '%2' }
120body:             |
121  bb.0.entry:
122    liveins: $x3, $f1, $x5
123
124    %2 = COPY $x5
125    %1 = COPY $f1
126    %0 = COPY $x3
127    %3 = LI8 443
128    STXSSPX %1, %0, killed %3, implicit $rm
129    ; CHECK: stfs {{[0-9]+}}, 443(3)
130    BLR8 implicit $lr8, implicit $rm
131...
132
133
134---
135name:            testSTXSDX
136alignment:       16
137exposesReturnsTwice: false
138legalized:       false
139regBankSelected: false
140selected:        false
141tracksRegLiveness: true
142registers:
143  - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
144  - { id: 1, class: vsfrc, preferred-register: '' }
145  - { id: 2, class: g8rc, preferred-register: '' }
146  - { id: 3, class: g8rc, preferred-register: '' }
147liveins:
148  - { reg: '$x3', virtual-reg: '%0' }
149  - { reg: '$f1', virtual-reg: '%1' }
150  - { reg: '$x5', virtual-reg: '%2' }
151body:             |
152  bb.0.entry:
153    liveins: $x3, $f1, $x5
154
155    %2 = COPY $x5
156    %1 = COPY $f1
157    %0 = COPY $x3
158    %3 = LI8  7
159    STXSDX %1, %0, killed %3, implicit $rm
160    ; CHECK: stfd {{[0-9]+}}, 7(3)
161    BLR8 implicit $lr8, implicit $rm
162...
163