xref: /llvm-project/llvm/test/CodeGen/PowerPC/combine_ext_trunc.ll (revision b922a3621116b404d868af8b74cab25ab78555be)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs | FileCheck %s
3
4; FIXME: We have implemented the following patterns in DAGCombiner.cpp,
5; but we can't get results as expected.
6
7; fold (or (and X, (xor Y, -1)), Y) to (or X, Y)
8define i32 @pattern1(i32 %x, i32 %y){
9; CHECK-LABEL: pattern1:
10; CHECK:       # %bb.0:
11; CHECK-NEXT:    xori 5, 4, 65535
12; CHECK-NEXT:    xoris 5, 5, 65535
13; CHECK-NEXT:    and 3, 3, 5
14; CHECK-NEXT:    or 3, 3, 4
15; CHECK-NEXT:    blr
16    %a = xor i32 %y, -1
17    %b = and i32 %x, %a
18    %c = or i32 %b, %y
19    ret i32 %c
20}
21
22; fold (or (and (xor Y, -1), X), Y) to (or X, Y)
23define i32 @pattern2(i32 %x, i32 %y){
24; CHECK-LABEL: pattern2:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    xori 5, 4, 65535
27; CHECK-NEXT:    xoris 5, 5, 65535
28; CHECK-NEXT:    and 3, 5, 3
29; CHECK-NEXT:    or 3, 3, 4
30; CHECK-NEXT:    blr
31    %a = xor i32 %y, -1
32    %b = and i32 %a, %x
33    %c = or i32 %b, %y
34    ret i32 %c
35}
36
37; fold (and (select Cond, 0, -1), X) to (select Cond, 0, X)
38define i32 @pattern3(i1 %cond, i32 %x) {
39; CHECK-LABEL: pattern3:
40; CHECK:       # %bb.0:
41; CHECK-NEXT:    andi. 3, 3, 1
42; CHECK-NEXT:    li 3, -1
43; CHECK-NEXT:    rldic 3, 3, 0, 32
44; CHECK-NEXT:    iselgt 3, 0, 3
45; CHECK-NEXT:    and 3, 3, 4
46; CHECK-NEXT:    blr
47  %sel = select i1 %cond, i32 0, i32 -1
48  %res = and i32 %sel, %x
49  ret i32 %res
50}
51
52; fold (or X, (select Cond, -1, 0)) to (select Cond, -1, X)
53define i32 @pattern4(i1 %cond, i32 %x) {
54; CHECK-LABEL: pattern4:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    andi. 3, 3, 1
57; CHECK-NEXT:    li 3, -1
58; CHECK-NEXT:    li 5, 0
59; CHECK-NEXT:    rldic 3, 3, 0, 32
60; CHECK-NEXT:    iselgt 3, 3, 5
61; CHECK-NEXT:    or 3, 4, 3
62; CHECK-NEXT:    blr
63  %sel = select i1 %cond, i32 -1, i32 0
64  %res = or i32 %x, %sel
65  ret i32 %res
66}
67