xref: /llvm-project/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll (revision 427fb35192f1f7bb694a5910b05abc5925a798b2) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
3; RUN:   -mcpu=pwr7 < %s | FileCheck %s
4
5declare i32 @llvm.ppc.mfspr.i32(i32 immarg)
6declare void @llvm.ppc.mtspr.i32(i32 immarg, i32)
7
8@ula = external dso_local global i32, align 4
9
10define dso_local i32 @test_mfxer() {
11; CHECK-LABEL: test_mfxer:
12; CHECK:       # %bb.0: # %entry
13; CHECK-NEXT:    mfxer 3
14; CHECK-NEXT:    blr
15entry:
16  %0 = call i32 @llvm.ppc.mfspr.i32(i32 1)
17  ret i32 %0
18}
19
20define dso_local i32 @test_mflr() {
21; CHECK-LABEL: test_mflr:
22; CHECK:       # %bb.0: # %entry
23; CHECK-NEXT:    mfspr 3, 8
24; CHECK-NEXT:    blr
25entry:
26  %0 = call i32 @llvm.ppc.mfspr.i32(i32 8)
27  ret i32 %0
28}
29
30define dso_local i32 @test_mfctr() {
31; CHECK-LABEL: test_mfctr:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    mfspr 3, 9
34; CHECK-NEXT:    blr
35entry:
36  %0 = call i32 @llvm.ppc.mfspr.i32(i32 9)
37  ret i32 %0
38}
39
40define dso_local i32 @test_mfppr() {
41; CHECK-LABEL: test_mfppr:
42; CHECK:       # %bb.0: # %entry
43; CHECK-NEXT:    mfspr 3, 896
44; CHECK-NEXT:    blr
45entry:
46  %0 = call i32 @llvm.ppc.mfspr.i32(i32 896)
47  ret i32 %0
48}
49
50define dso_local i32 @test_mfppr32() {
51; CHECK-LABEL: test_mfppr32:
52; CHECK:       # %bb.0: # %entry
53; CHECK-NEXT:    mfspr 3, 898
54; CHECK-NEXT:    blr
55entry:
56  %0 = call i32 @llvm.ppc.mfspr.i32(i32 898)
57  ret i32 %0
58}
59
60define dso_local void @test_mtxer() {
61; CHECK-LABEL: test_mtxer:
62; CHECK:       # %bb.0: # %entry
63; CHECK-NEXT:    lwz 3, L..C0(2) # @ula
64; CHECK-NEXT:    lwz 3, 0(3)
65; CHECK-NEXT:    mtxer 3
66; CHECK-NEXT:    blr
67entry:
68  %0 = load i32, ptr @ula, align 8
69  tail call void @llvm.ppc.mtspr.i32(i32 1, i32 %0)
70  ret void
71}
72
73define dso_local void @test_mtlr() {
74; CHECK-LABEL: test_mtlr:
75; CHECK:       # %bb.0: # %entry
76; CHECK-NEXT:    lwz 3, L..C0(2) # @ula
77; CHECK-NEXT:    lwz 3, 0(3)
78; CHECK-NEXT:    mtspr 8, 3
79; CHECK-NEXT:    blr
80entry:
81  %0 = load i32, ptr @ula, align 8
82  tail call void @llvm.ppc.mtspr.i32(i32 8, i32 %0)
83  ret void
84}
85
86define dso_local void @test_mtctr() {
87; CHECK-LABEL: test_mtctr:
88; CHECK:       # %bb.0: # %entry
89; CHECK-NEXT:    lwz 3, L..C0(2) # @ula
90; CHECK-NEXT:    lwz 3, 0(3)
91; CHECK-NEXT:    mtspr 9, 3
92; CHECK-NEXT:    blr
93entry:
94  %0 = load i32, ptr @ula, align 8
95  tail call void @llvm.ppc.mtspr.i32(i32 9, i32 %0)
96  ret void
97}
98
99define dso_local void @test_mtppr() {
100; CHECK-LABEL: test_mtppr:
101; CHECK:       # %bb.0: # %entry
102; CHECK-NEXT:    lwz 3, L..C0(2) # @ula
103; CHECK-NEXT:    lwz 3, 0(3)
104; CHECK-NEXT:    mtspr 896, 3
105; CHECK-NEXT:    blr
106entry:
107  %0 = load i32, ptr @ula, align 8
108  tail call void @llvm.ppc.mtspr.i32(i32 896, i32 %0)
109  ret void
110}
111
112define dso_local void @test_mtppr32() {
113; CHECK-LABEL: test_mtppr32:
114; CHECK:       # %bb.0: # %entry
115; CHECK-NEXT:    lwz 3, L..C0(2) # @ula
116; CHECK-NEXT:    lwz 3, 0(3)
117; CHECK-NEXT:    mtspr 898, 3
118; CHECK-NEXT:    blr
119entry:
120  %0 = load i32, ptr @ula, align 8
121  tail call void @llvm.ppc.mtspr.i32(i32 898, i32 %0)
122  ret void
123}
124