xref: /llvm-project/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll (revision 427fb35192f1f7bb694a5910b05abc5925a798b2) 
1; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
2; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64B
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
4; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
5; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
6; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32B
7; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
8; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
9
10@us = external global i16, align 2
11@us_addr = external global ptr, align 8
12@ui = external global i32, align 4
13@ui_addr = external global ptr, align 8
14
15define dso_local void @test_builtin_ppc_store2r() {
16; CHECK-64B-LABEL: test_builtin_ppc_store2r:
17; CHECK-64B:         sthbrx 3, 0, 4
18; CHECK-64B-NEXT:    blr
19
20; CHECK-32B-LABEL: test_builtin_ppc_store2r:
21; CHECK-32B:         sthbrx 3, 0, 4
22; CHECK-32B-NEXT:    blr
23entry:
24  %0 = load i16, ptr @us, align 2
25  %conv = zext i16 %0 to i32
26  %1 = load ptr, ptr @us_addr, align 8
27  call void @llvm.ppc.store2r(i32 %conv, ptr %1)
28  ret void
29}
30
31declare void @llvm.ppc.store2r(i32, ptr)
32
33define dso_local void @test_builtin_ppc_store4r() {
34; CHECK-64B-LABEL: test_builtin_ppc_store4r:
35; CHECK-64B:         stwbrx 3, 0, 4
36; CHECK-64B-NEXT:    blr
37
38; CHECK-32B-LABEL: test_builtin_ppc_store4r:
39; CHECK-32B:         stwbrx 3, 0, 4
40; CHECK-32B-NEXT:    blr
41entry:
42  %0 = load i32, ptr @ui, align 4
43  %1 = load ptr, ptr @ui_addr, align 8
44  call void @llvm.ppc.store4r(i32 %0, ptr %1)
45  ret void
46}
47
48declare void @llvm.ppc.store4r(i32, ptr)
49
50define dso_local zeroext i16 @test_builtin_ppc_load2r() {
51; CHECK-64B-LABEL: test_builtin_ppc_load2r:
52; CHECK-64B:         lhbrx 3, 0, 3
53; CHECK-64B-NEXT:    blr
54
55; CHECK-32B-LABEL: test_builtin_ppc_load2r:
56; CHECK-32B:         lhbrx 3, 0, 3
57; CHECK-32B-NEXT:    blr
58entry:
59  %0 = load ptr, ptr @us_addr, align 8
60  %1 = call i32 @llvm.ppc.load2r(ptr %0)
61  %conv = trunc i32 %1 to i16
62  ret i16 %conv
63}
64
65define dso_local signext i16 @test_builtin_ppc_load2r_signext() {
66; CHECK-64B-LABEL: test_builtin_ppc_load2r_signext:
67; CHECK-64B:         lhbrx 3, 0, 3
68; CHECK-64B-NEXT:    extsh 3, 3
69; CHECK-64B-NEXT:    blr
70
71; CHECK-32B-LABEL: test_builtin_ppc_load2r_signext:
72; CHECK-32B:         lhbrx 3, 0, 3
73; CHECK-32B-NEXT:    extsh 3, 3
74; CHECK-32B-NEXT:    blr
75entry:
76  %0 = load ptr, ptr @us_addr, align 8
77  %1 = call i32 @llvm.ppc.load2r(ptr %0)
78  %conv = trunc i32 %1 to i16
79  ret i16 %conv
80}
81
82declare i32 @llvm.ppc.load2r(ptr)
83
84define dso_local zeroext i32 @test_builtin_ppc_load4r() {
85; CHECK-64B-LABEL: test_builtin_ppc_load4r:
86; CHECK-64B:         lwbrx 3, 0, 3
87; CHECK-64B-NEXT:    blr
88
89; CHECK-32B-LABEL: test_builtin_ppc_load4r:
90; CHECK-32B:         lwbrx 3, 0, 3
91; CHECK-32B-NEXT:    blr
92entry:
93  %0 = load ptr, ptr @ui_addr, align 8
94  %1 = call i32 @llvm.ppc.load4r(ptr %0)
95  ret i32 %1
96}
97
98declare i32 @llvm.ppc.load4r(ptr)
99