1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux \ 3; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s 4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \ 5; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s 6 7define i64 @cdtbcd_test(i64 noundef %ll) { 8; CHECK-LABEL: cdtbcd_test: 9; CHECK: # %bb.0: # %entry 10; CHECK-NEXT: cdtbcd r3, r3 11; CHECK-NEXT: blr 12entry: 13 %0 = tail call i64 @llvm.ppc.cdtbcdd(i64 %ll) 14 ret i64 %0 15} 16 17define zeroext i32 @cdtbcd_test_ui(i32 noundef zeroext %ui) { 18; CHECK-LABEL: cdtbcd_test_ui: 19; CHECK: # %bb.0: # %entry 20; CHECK-NEXT: cdtbcd r3, r3 21; CHECK-NEXT: clrldi r3, r3, 32 22; CHECK-NEXT: blr 23entry: 24 %conv = zext i32 %ui to i64 25 %0 = tail call i64 @llvm.ppc.cdtbcdd(i64 %conv) 26 %conv1 = trunc i64 %0 to i32 27 ret i32 %conv1 28} 29 30define i64 @cbcdtd_test(i64 noundef %ll) { 31; CHECK-LABEL: cbcdtd_test: 32; CHECK: # %bb.0: # %entry 33; CHECK-NEXT: cbcdtd r3, r3 34; CHECK-NEXT: blr 35entry: 36 %0 = tail call i64 @llvm.ppc.cbcdtdd(i64 %ll) 37 ret i64 %0 38} 39 40define zeroext i32 @cbcdtd_test_ui(i32 noundef zeroext %ui) { 41; CHECK-LABEL: cbcdtd_test_ui: 42; CHECK: # %bb.0: # %entry 43; CHECK-NEXT: cbcdtd r3, r3 44; CHECK-NEXT: clrldi r3, r3, 32 45; CHECK-NEXT: blr 46entry: 47 %conv = zext i32 %ui to i64 48 %0 = tail call i64 @llvm.ppc.cbcdtdd(i64 %conv) 49 %conv1 = trunc i64 %0 to i32 50 ret i32 %conv1 51} 52 53define i64 @addg6s_test(i64 noundef %ll, i64 noundef %ll2) { 54; CHECK-LABEL: addg6s_test: 55; CHECK: # %bb.0: # %entry 56; CHECK-NEXT: addg6s r3, r3, r4 57; CHECK-NEXT: blr 58entry: 59 %0 = tail call i64 @llvm.ppc.addg6sd(i64 %ll, i64 %ll2) 60 ret i64 %0 61} 62 63define zeroext i32 @addg6s_test_ui(i32 noundef zeroext %ui, i32 noundef zeroext %ui2) { 64; CHECK-LABEL: addg6s_test_ui: 65; CHECK: # %bb.0: # %entry 66; CHECK-NEXT: addg6s r3, r3, r4 67; CHECK-NEXT: clrldi r3, r3, 32 68; CHECK-NEXT: blr 69entry: 70 %conv = zext i32 %ui to i64 71 %conv1 = zext i32 %ui2 to i64 72 %0 = tail call i64 @llvm.ppc.addg6sd(i64 %conv, i64 %conv1) 73 %conv2 = trunc i64 %0 to i32 74 ret i32 %conv2 75} 76 77declare i64 @llvm.ppc.cdtbcdd(i64) 78declare i64 @llvm.ppc.cbcdtdd(i64) 79declare i64 @llvm.ppc.addg6sd(i64, i64) 80