xref: /llvm-project/llvm/test/CodeGen/PowerPC/branch_coalescing.mir (revision 112fba974ce42a6e552f7391d20a858a128283a1)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
2# RUN: llc -o - %s -run-pass=ppc-branch-coalescing | FileCheck %s
3--- |
4  target triple = "powerpc64le-unknown-linux-gnu"
5
6  define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
7    unreachable
8  }
9...
10---
11name:            testBranchCoal
12alignment:       16
13tracksRegLiveness: true
14liveins:
15  - { reg: '$f1', virtual-reg: '%0' }
16  - { reg: '$f2', virtual-reg: '%1' }
17  - { reg: '$f3', virtual-reg: '%2' }
18  - { reg: '$x6', virtual-reg: '%3' }
19frameInfo:
20  maxAlignment:    1
21constants:
22  - id:              0
23    value:           double 2.000000e-03
24    alignment:       8
25  - id:              1
26    value:           double 5.000000e-03
27    alignment:       8
28machineFunctionInfo: {}
29body:             |
30  ; CHECK-LABEL: name: testBranchCoal
31  ; CHECK: bb.0:
32  ; CHECK-NEXT:   successors: %bb.1(0x1c71c71d), %bb.6(0x638e38e3)
33  ; CHECK-NEXT:   liveins: $f1, $f2, $f3, $x2, $x6
34  ; CHECK-NEXT: {{  $}}
35  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:g8rc = COPY $x6
36  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:f8rc = COPY $f3
37  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:f8rc = COPY $f2
38  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:f8rc = COPY $f1
39  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
40  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x2
41  ; CHECK-NEXT:   [[CMPLWI:%[0-9]+]]:crrc = CMPLWI killed [[COPY4]], 0
42  ; CHECK-NEXT:   [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 [[COPY5]], %const.0
43  ; CHECK-NEXT:   [[LFD:%[0-9]+]]:f8rc = LFD target-flags(ppc-toc-lo) %const.0, killed [[ADDIStocHA8_]] :: (load (s64) from constant-pool)
44  ; CHECK-NEXT:   [[XXLXORdpz:%[0-9]+]]:f8rc = XXLXORdpz
45  ; CHECK-NEXT:   [[ADDIStocHA8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 [[COPY5]], %const.1
46  ; CHECK-NEXT:   [[LFD1:%[0-9]+]]:f8rc = LFD target-flags(ppc-toc-lo) %const.1, killed [[ADDIStocHA8_1]] :: (load (s64) from constant-pool)
47  ; CHECK-NEXT:   BCC 76, [[CMPLWI]], %bb.6
48  ; CHECK-NEXT: {{  $}}
49  ; CHECK-NEXT: bb.1:
50  ; CHECK-NEXT:   successors: %bb.6(0x80000000)
51  ; CHECK-NEXT: {{  $}}
52  ; CHECK-NEXT: bb.6:
53  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:f8rc = PHI [[LFD]], %bb.1, [[COPY3]], %bb.0
54  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:f8rc = PHI [[XXLXORdpz]], %bb.1, [[COPY2]], %bb.0
55  ; CHECK-NEXT:   [[PHI2:%[0-9]+]]:f8rc = PHI [[LFD1]], %bb.1, [[COPY1]], %bb.0
56  ; CHECK-NEXT:   [[XSADDDP:%[0-9]+]]:vsfrc = nofpexcept XSADDDP killed [[PHI]], killed [[PHI1]], implicit $rm
57  ; CHECK-NEXT:   [[XSADDDP1:%[0-9]+]]:vsfrc = nofpexcept XSADDDP killed [[XSADDDP]], killed [[PHI2]], implicit $rm
58  ; CHECK-NEXT:   $f1 = COPY [[XSADDDP1]]
59  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $f1
60  bb.0:
61    successors: %bb.1, %bb.2
62    liveins: $f1, $f2, $f3, $x2, $x6
63
64    %3:g8rc = COPY $x6
65    %2:f8rc = COPY $f3
66    %1:f8rc = COPY $f2
67    %0:f8rc = COPY $f1
68    %4:gprc = COPY %3.sub_32
69    %16:g8rc_and_g8rc_nox0 = COPY $x2
70    %5:crrc = CMPLWI killed %4, 0
71    %6:g8rc_and_g8rc_nox0 = ADDIStocHA8 %16, %const.0
72    %7:f8rc = LFD target-flags(ppc-toc-lo) %const.0, killed %6 :: (load (s64) from constant-pool)
73    BCC 76, %5, %bb.2
74
75  bb.1:
76
77  bb.2:
78    successors: %bb.3, %bb.4
79
80    %8:f8rc = PHI %7, %bb.1, %0, %bb.0
81    %9:f8rc = XXLXORdpz
82    BCC 76, %5, %bb.4
83
84  bb.3:
85
86  bb.4:
87    successors: %bb.5, %bb.6
88
89    %10:f8rc = PHI %9, %bb.3, %1, %bb.2
90    %11:g8rc_and_g8rc_nox0 = ADDIStocHA8 %16, %const.1
91    %12:f8rc = LFD target-flags(ppc-toc-lo) %const.1, killed %11 :: (load (s64) from constant-pool)
92    BCC 76, %5, %bb.6
93
94  bb.5:
95
96  bb.6:
97    %13:f8rc = PHI %12, %bb.5, %2, %bb.4
98    %14:vsfrc = nofpexcept XSADDDP killed %8, killed %10, implicit $rm
99    %15:vsfrc = nofpexcept XSADDDP killed %14, killed %13, implicit $rm
100    $f1 = COPY %15
101    BLR8 implicit $lr8, implicit $rm, implicit $f1
102
103...
104