xref: /llvm-project/llvm/test/CodeGen/PowerPC/and_sext.ll (revision 31fb0ae23d3d1a1b90198a68c80c9116d844a01f)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; These tests should not contain a sign extend.
3; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | FileCheck %s
4; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep extsh
5; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep extsb
6
7define i32 @test1(i32 %mode.0.i.0) {
8; CHECK-LABEL: test1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    rlwinm 3, 3, 0, 27, 28
11; CHECK-NEXT:    blr
12  %tmp.79 = trunc i32 %mode.0.i.0 to i16
13  %tmp.80 = sext i16 %tmp.79 to i32
14  %tmp.81 = and i32 %tmp.80, 24
15  ret i32 %tmp.81
16}
17
18define signext i16 @test2(i16 signext %X, i16 signext %x)  {
19; CHECK-LABEL: test2:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    add 3, 3, 4
22; CHECK-NEXT:    srawi 3, 3, 1
23; CHECK-NEXT:    blr
24  %tmp = sext i16 %X to i32
25  %tmp1 = sext i16 %x to i32
26  %tmp2 = add i32 %tmp, %tmp1
27  %tmp4 = ashr i32 %tmp2, 1
28  %tmp5 = trunc i32 %tmp4 to i16
29  %tmp45 = sext i16 %tmp5 to i32
30  %retval = trunc i32 %tmp45 to i16
31  ret i16 %retval
32}
33
34define signext i16 @test3(i32 zeroext %X)  {
35; CHECK-LABEL: test3:
36; CHECK:       # %bb.0:
37; CHECK-NEXT:    srawi 3, 3, 16
38; CHECK-NEXT:    blr
39  %tmp1 = lshr i32 %X, 16
40  %tmp2 = trunc i32 %tmp1 to i16
41  ret i16 %tmp2
42}
43
44