1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 \ 3; RUN: -verify-machineinstrs -O2 -mattr=vsx < %s | \ 4; RUN: FileCheck %s --check-prefix=CHECK-AIX 5; RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 \ 6; RUN: -verify-machineinstrs -O2 -mattr=vsx < %s | \ 7; RUN: FileCheck %s 8 9define void @test_aix_splatimm(i32 %arg, i32 %arg1, i32 %arg2) { 10; CHECK-AIX-LABEL: test_aix_splatimm: 11; CHECK-AIX: # %bb.0: # %bb 12; CHECK-AIX-NEXT: bclr 12, 20, 0 13; CHECK-AIX-NEXT: # %bb.1: # %bb3 14; CHECK-AIX-NEXT: slwi 3, 3, 8 15; CHECK-AIX-NEXT: neg 3, 3 16; CHECK-AIX-NEXT: lwz 6, 0(3) 17; CHECK-AIX-NEXT: sldi 3, 3, 48 18; CHECK-AIX-NEXT: std 3, -16(1) 19; CHECK-AIX-NEXT: std 3, -8(1) 20; CHECK-AIX-NEXT: addi 3, 1, -16 21; CHECK-AIX-NEXT: lxvw4x 34, 0, 3 22; CHECK-AIX-NEXT: srwi 3, 4, 16 23; CHECK-AIX-NEXT: srwi 4, 5, 16 24; CHECK-AIX-NEXT: mullw 3, 4, 3 25; CHECK-AIX-NEXT: srwi 4, 6, 1 26; CHECK-AIX-NEXT: mullw 3, 3, 4 27; CHECK-AIX-NEXT: li 4, 0 28; CHECK-AIX-NEXT: neg 3, 3 29; CHECK-AIX-NEXT: sldi 3, 3, 48 30; CHECK-AIX-NEXT: vsplth 2, 2, 0 31; CHECK-AIX-NEXT: stxvw4x 34, 0, 4 32; CHECK-AIX-NEXT: std 3, -32(1) 33; CHECK-AIX-NEXT: std 3, -24(1) 34; CHECK-AIX-NEXT: addi 3, 1, -32 35; CHECK-AIX-NEXT: lxvw4x 34, 0, 3 36; CHECK-AIX-NEXT: vsplth 2, 2, 0 37; CHECK-AIX-NEXT: stxvw4x 34, 0, 3 38; 39; CHECK-LABEL: test_aix_splatimm: 40; CHECK: # %bb.0: # %bb 41; CHECK-NEXT: bclr 12, 20, 0 42; CHECK-NEXT: # %bb.1: # %bb3 43; CHECK-NEXT: slwi 3, 3, 8 44; CHECK-NEXT: srwi 4, 4, 16 45; CHECK-NEXT: neg 3, 3 46; CHECK-NEXT: srwi 5, 5, 16 47; CHECK-NEXT: mullw 4, 5, 4 48; CHECK-NEXT: lwz 5, 0(3) 49; CHECK-NEXT: mtvsrd 34, 3 50; CHECK-NEXT: li 3, 0 51; CHECK-NEXT: srwi 5, 5, 1 52; CHECK-NEXT: mullw 4, 4, 5 53; CHECK-NEXT: neg 4, 4 54; CHECK-NEXT: mtvsrd 35, 4 55; CHECK-NEXT: vsplth 2, 2, 3 56; CHECK-NEXT: stxvd2x 34, 0, 3 57; CHECK-NEXT: vsplth 3, 3, 3 58; CHECK-NEXT: stxvd2x 35, 0, 3 59bb: 60 br i1 undef, label %bb22, label %bb3 61 62bb3: ; preds = %bb 63 %i = insertelement <8 x i16> undef, i16 0, i32 0 64 %i4 = trunc i32 %arg to i16 65 %i5 = mul i16 %i4, -256 66 %i6 = insertelement <8 x i16> %i, i16 %i5, i32 1 67 %i7 = ashr i32 %arg1, 16 68 %i8 = ashr i32 %arg2, 16 69 %i9 = mul nsw i32 %i8, %i7 70 %i10 = insertelement <8 x i16> %i6, i16 0, i32 2 71 %i11 = insertelement <8 x i16> %i10, i16 0, i32 3 72 %i12 = load i32, ptr undef, align 4 73 %i13 = ashr i32 %i12, 1 74 %i14 = mul i32 %i9, %i13 75 %i15 = trunc i32 %i14 to i16 76 %i16 = sub i16 0, %i15 77 %i17 = insertelement <8 x i16> %i11, i16 %i16, i32 4 78 %i18 = insertelement <8 x i16> %i17, i16 0, i32 5 79 %i19 = bitcast <8 x i16> %i18 to <16 x i8> 80 %i20 = shufflevector <16 x i8> %i19, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3> 81 store <16 x i8> %i20, ptr null, align 16 82 %i21 = shufflevector <16 x i8> %i19, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9> 83 store <16 x i8> %i21, ptr undef, align 16 84 unreachable 85 86bb22: ; preds = %bb 87 ret void 88} 89