1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64 3; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32 4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-64-P10 5; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-32-P10 6 7; Byte indexed 8 9define <16 x i8> @testByte(<16 x i8> %a, i64 %b, i64 %idx) { 10; CHECK-64-LABEL: testByte: 11; CHECK-64: # %bb.0: # %entry 12; CHECK-64-NEXT: addi 5, 1, -16 13; CHECK-64-NEXT: clrldi 4, 4, 60 14; CHECK-64-NEXT: stxv 34, -16(1) 15; CHECK-64-NEXT: stbx 3, 5, 4 16; CHECK-64-NEXT: lxv 34, -16(1) 17; CHECK-64-NEXT: blr 18; 19; CHECK-32-LABEL: testByte: 20; CHECK-32: # %bb.0: # %entry 21; CHECK-32-NEXT: addi 5, 1, -16 22; CHECK-32-NEXT: clrlwi 3, 6, 28 23; CHECK-32-NEXT: stxv 34, -16(1) 24; CHECK-32-NEXT: stbx 4, 5, 3 25; CHECK-32-NEXT: lxv 34, -16(1) 26; CHECK-32-NEXT: blr 27; 28; CHECK-64-P10-LABEL: testByte: 29; CHECK-64-P10: # %bb.0: # %entry 30; CHECK-64-P10-NEXT: vinsblx 2, 4, 3 31; CHECK-64-P10-NEXT: blr 32; 33; CHECK-32-P10-LABEL: testByte: 34; CHECK-32-P10: # %bb.0: # %entry 35; CHECK-32-P10-NEXT: vinsblx 2, 6, 4 36; CHECK-32-P10-NEXT: blr 37entry: 38 %conv = trunc i64 %b to i8 39 %vecins = insertelement <16 x i8> %a, i8 %conv, i64 %idx 40 ret <16 x i8> %vecins 41} 42 43; Halfword indexed 44 45define <8 x i16> @testHalf(<8 x i16> %a, i64 %b, i64 %idx) { 46; CHECK-64-LABEL: testHalf: 47; CHECK-64: # %bb.0: # %entry 48; CHECK-64-NEXT: addi 5, 1, -16 49; CHECK-64-NEXT: rlwinm 4, 4, 1, 28, 30 50; CHECK-64-NEXT: stxv 34, -16(1) 51; CHECK-64-NEXT: sthx 3, 5, 4 52; CHECK-64-NEXT: lxv 34, -16(1) 53; CHECK-64-NEXT: blr 54; 55; CHECK-32-LABEL: testHalf: 56; CHECK-32: # %bb.0: # %entry 57; CHECK-32-NEXT: addi 5, 1, -16 58; CHECK-32-NEXT: rlwinm 3, 6, 1, 28, 30 59; CHECK-32-NEXT: stxv 34, -16(1) 60; CHECK-32-NEXT: sthx 4, 5, 3 61; CHECK-32-NEXT: lxv 34, -16(1) 62; CHECK-32-NEXT: blr 63; 64; CHECK-64-P10-LABEL: testHalf: 65; CHECK-64-P10: # %bb.0: # %entry 66; CHECK-64-P10-NEXT: slwi 4, 4, 1 67; CHECK-64-P10-NEXT: vinshlx 2, 4, 3 68; CHECK-64-P10-NEXT: blr 69; 70; CHECK-32-P10-LABEL: testHalf: 71; CHECK-32-P10: # %bb.0: # %entry 72; CHECK-32-P10-NEXT: slwi 3, 6, 1 73; CHECK-32-P10-NEXT: vinshlx 2, 3, 4 74; CHECK-32-P10-NEXT: blr 75entry: 76 %conv = trunc i64 %b to i16 77 %vecins = insertelement <8 x i16> %a, i16 %conv, i64 %idx 78 ret <8 x i16> %vecins 79} 80 81; Word indexed 82 83define <4 x i32> @testWord(<4 x i32> %a, i64 %b, i64 %idx) { 84; CHECK-64-LABEL: testWord: 85; CHECK-64: # %bb.0: # %entry 86; CHECK-64-NEXT: addi 5, 1, -16 87; CHECK-64-NEXT: rlwinm 4, 4, 2, 28, 29 88; CHECK-64-NEXT: stxv 34, -16(1) 89; CHECK-64-NEXT: stwx 3, 5, 4 90; CHECK-64-NEXT: lxv 34, -16(1) 91; CHECK-64-NEXT: blr 92; 93; CHECK-32-LABEL: testWord: 94; CHECK-32: # %bb.0: # %entry 95; CHECK-32-NEXT: addi 5, 1, -16 96; CHECK-32-NEXT: rlwinm 3, 6, 2, 28, 29 97; CHECK-32-NEXT: stxv 34, -16(1) 98; CHECK-32-NEXT: stwx 4, 5, 3 99; CHECK-32-NEXT: lxv 34, -16(1) 100; CHECK-32-NEXT: blr 101; 102; CHECK-64-P10-LABEL: testWord: 103; CHECK-64-P10: # %bb.0: # %entry 104; CHECK-64-P10-NEXT: slwi 4, 4, 2 105; CHECK-64-P10-NEXT: vinswlx 2, 4, 3 106; CHECK-64-P10-NEXT: blr 107; 108; CHECK-32-P10-LABEL: testWord: 109; CHECK-32-P10: # %bb.0: # %entry 110; CHECK-32-P10-NEXT: slwi 3, 6, 2 111; CHECK-32-P10-NEXT: vinswlx 2, 3, 4 112; CHECK-32-P10-NEXT: blr 113entry: 114 %conv = trunc i64 %b to i32 115 %vecins = insertelement <4 x i32> %a, i32 %conv, i64 %idx 116 ret <4 x i32> %vecins 117} 118 119; Word immediate 120 121define <4 x i32> @testWordImm(<4 x i32> %a, i64 %b) { 122; CHECK-64-LABEL: testWordImm: 123; CHECK-64: # %bb.0: # %entry 124; CHECK-64-NEXT: mtfprwz 0, 3 125; CHECK-64-NEXT: xxinsertw 34, 0, 4 126; CHECK-64-NEXT: xxinsertw 34, 0, 12 127; CHECK-64-NEXT: blr 128; 129; CHECK-32-LABEL: testWordImm: 130; CHECK-32: # %bb.0: # %entry 131; CHECK-32-NEXT: mtfprwz 0, 4 132; CHECK-32-NEXT: xxinsertw 34, 0, 4 133; CHECK-32-NEXT: xxinsertw 34, 0, 12 134; CHECK-32-NEXT: blr 135; 136; CHECK-64-P10-LABEL: testWordImm: 137; CHECK-64-P10: # %bb.0: # %entry 138; CHECK-64-P10-NEXT: vinsw 2, 3, 4 139; CHECK-64-P10-NEXT: vinsw 2, 3, 12 140; CHECK-64-P10-NEXT: blr 141; 142; CHECK-32-P10-LABEL: testWordImm: 143; CHECK-32-P10: # %bb.0: # %entry 144; CHECK-32-P10-NEXT: vinsw 2, 4, 4 145; CHECK-32-P10-NEXT: vinsw 2, 4, 12 146; CHECK-32-P10-NEXT: blr 147entry: 148 %conv = trunc i64 %b to i32 149 %vecins = insertelement <4 x i32> %a, i32 %conv, i32 1 150 %vecins2 = insertelement <4 x i32> %vecins, i32 %conv, i32 3 151 ret <4 x i32> %vecins2 152} 153 154; Doubleword indexed 155 156define <2 x i64> @testDoubleword(<2 x i64> %a, i64 %b, i64 %idx) { 157; CHECK-64-LABEL: testDoubleword: 158; CHECK-64: # %bb.0: # %entry 159; CHECK-64-NEXT: addi 5, 1, -16 160; CHECK-64-NEXT: rlwinm 4, 4, 3, 28, 28 161; CHECK-64-NEXT: stxv 34, -16(1) 162; CHECK-64-NEXT: stdx 3, 5, 4 163; CHECK-64-NEXT: lxv 34, -16(1) 164; CHECK-64-NEXT: blr 165; 166; CHECK-32-LABEL: testDoubleword: 167; CHECK-32: # %bb.0: # %entry 168; CHECK-32-NEXT: add 5, 6, 6 169; CHECK-32-NEXT: addi 7, 1, -32 170; CHECK-32-NEXT: stxv 34, -32(1) 171; CHECK-32-NEXT: rlwinm 6, 5, 2, 28, 29 172; CHECK-32-NEXT: stwx 3, 7, 6 173; CHECK-32-NEXT: addi 3, 5, 1 174; CHECK-32-NEXT: addi 5, 1, -16 175; CHECK-32-NEXT: lxv 0, -32(1) 176; CHECK-32-NEXT: rlwinm 3, 3, 2, 28, 29 177; CHECK-32-NEXT: stxv 0, -16(1) 178; CHECK-32-NEXT: stwx 4, 5, 3 179; CHECK-32-NEXT: lxv 34, -16(1) 180; CHECK-32-NEXT: blr 181; 182; CHECK-64-P10-LABEL: testDoubleword: 183; CHECK-64-P10: # %bb.0: # %entry 184; CHECK-64-P10-NEXT: rlwinm 4, 4, 3, 0, 28 185; CHECK-64-P10-NEXT: vinsdlx 2, 4, 3 186; CHECK-64-P10-NEXT: blr 187; 188; CHECK-32-P10-LABEL: testDoubleword: 189; CHECK-32-P10: # %bb.0: # %entry 190; CHECK-32-P10-NEXT: add 5, 6, 6 191; CHECK-32-P10-NEXT: slwi 6, 5, 2 192; CHECK-32-P10-NEXT: vinswlx 2, 6, 3 193; CHECK-32-P10-NEXT: addi 3, 5, 1 194; CHECK-32-P10-NEXT: slwi 3, 3, 2 195; CHECK-32-P10-NEXT: vinswlx 2, 3, 4 196; CHECK-32-P10-NEXT: blr 197entry: 198 %vecins = insertelement <2 x i64> %a, i64 %b, i64 %idx 199 ret <2 x i64> %vecins 200} 201 202; Doubleword immediate 203 204define <2 x i64> @testDoublewordImm(<2 x i64> %a, i64 %b) { 205; CHECK-64-LABEL: testDoublewordImm: 206; CHECK-64: # %bb.0: # %entry 207; CHECK-64-NEXT: mtfprd 0, 3 208; CHECK-64-NEXT: xxmrghd 34, 34, 0 209; CHECK-64-NEXT: blr 210; 211; CHECK-32-LABEL: testDoublewordImm: 212; CHECK-32: # %bb.0: # %entry 213; CHECK-32-NEXT: mtfprwz 0, 3 214; CHECK-32-NEXT: xxinsertw 34, 0, 8 215; CHECK-32-NEXT: mtfprwz 0, 4 216; CHECK-32-NEXT: xxinsertw 34, 0, 12 217; CHECK-32-NEXT: blr 218; 219; CHECK-64-P10-LABEL: testDoublewordImm: 220; CHECK-64-P10: # %bb.0: # %entry 221; CHECK-64-P10-NEXT: vinsd 2, 3, 8 222; CHECK-64-P10-NEXT: blr 223; 224; CHECK-32-P10-LABEL: testDoublewordImm: 225; CHECK-32-P10: # %bb.0: # %entry 226; CHECK-32-P10-NEXT: vinsw 2, 3, 8 227; CHECK-32-P10-NEXT: vinsw 2, 4, 12 228; CHECK-32-P10-NEXT: blr 229entry: 230 %vecins = insertelement <2 x i64> %a, i64 %b, i32 1 231 ret <2 x i64> %vecins 232} 233 234define <2 x i64> @testDoublewordImm2(<2 x i64> %a, i64 %b) { 235; CHECK-64-LABEL: testDoublewordImm2: 236; CHECK-64: # %bb.0: # %entry 237; CHECK-64-NEXT: mtfprd 0, 3 238; CHECK-64-NEXT: xxpermdi 34, 0, 34, 1 239; CHECK-64-NEXT: blr 240; 241; CHECK-32-LABEL: testDoublewordImm2: 242; CHECK-32: # %bb.0: # %entry 243; CHECK-32-NEXT: mtfprwz 0, 3 244; CHECK-32-NEXT: xxinsertw 34, 0, 0 245; CHECK-32-NEXT: mtfprwz 0, 4 246; CHECK-32-NEXT: xxinsertw 34, 0, 4 247; CHECK-32-NEXT: blr 248; 249; CHECK-64-P10-LABEL: testDoublewordImm2: 250; CHECK-64-P10: # %bb.0: # %entry 251; CHECK-64-P10-NEXT: vinsd 2, 3, 0 252; CHECK-64-P10-NEXT: blr 253; 254; CHECK-32-P10-LABEL: testDoublewordImm2: 255; CHECK-32-P10: # %bb.0: # %entry 256; CHECK-32-P10-NEXT: vinsw 2, 3, 0 257; CHECK-32-P10-NEXT: vinsw 2, 4, 4 258; CHECK-32-P10-NEXT: blr 259entry: 260 %vecins = insertelement <2 x i64> %a, i64 %b, i32 0 261 ret <2 x i64> %vecins 262} 263 264; Float indexed 265 266define <4 x float> @testFloat1(<4 x float> %a, float %b, i32 zeroext %idx1) { 267; CHECK-64-LABEL: testFloat1: 268; CHECK-64: # %bb.0: # %entry 269; CHECK-64-NEXT: rlwinm 3, 4, 2, 28, 29 270; CHECK-64-NEXT: addi 4, 1, -16 271; CHECK-64-NEXT: stxv 34, -16(1) 272; CHECK-64-NEXT: stfsx 1, 4, 3 273; CHECK-64-NEXT: lxv 34, -16(1) 274; CHECK-64-NEXT: blr 275; 276; CHECK-32-LABEL: testFloat1: 277; CHECK-32: # %bb.0: # %entry 278; CHECK-32-NEXT: rlwinm 3, 4, 2, 28, 29 279; CHECK-32-NEXT: addi 4, 1, -16 280; CHECK-32-NEXT: stxv 34, -16(1) 281; CHECK-32-NEXT: stfsx 1, 4, 3 282; CHECK-32-NEXT: lxv 34, -16(1) 283; CHECK-32-NEXT: blr 284; 285; CHECK-64-P10-LABEL: testFloat1: 286; CHECK-64-P10: # %bb.0: # %entry 287; CHECK-64-P10-NEXT: xscvdpspn 35, 1 288; CHECK-64-P10-NEXT: slwi 3, 4, 2 289; CHECK-64-P10-NEXT: vinswvlx 2, 3, 3 290; CHECK-64-P10-NEXT: blr 291; 292; CHECK-32-P10-LABEL: testFloat1: 293; CHECK-32-P10: # %bb.0: # %entry 294; CHECK-32-P10-NEXT: xscvdpspn 35, 1 295; CHECK-32-P10-NEXT: slwi 3, 4, 2 296; CHECK-32-P10-NEXT: vinswvlx 2, 3, 3 297; CHECK-32-P10-NEXT: blr 298entry: 299 %vecins = insertelement <4 x float> %a, float %b, i32 %idx1 300 ret <4 x float> %vecins 301} 302 303define <4 x float> @testFloat2(<4 x float> %a, ptr %b, i32 zeroext %idx1, i32 zeroext %idx2) { 304; CHECK-64-LABEL: testFloat2: 305; CHECK-64: # %bb.0: # %entry 306; CHECK-64-NEXT: lwz 6, 0(3) 307; CHECK-64-NEXT: addi 7, 1, -16 308; CHECK-64-NEXT: rlwinm 4, 4, 2, 28, 29 309; CHECK-64-NEXT: stxv 34, -16(1) 310; CHECK-64-NEXT: rlwinm 5, 5, 2, 28, 29 311; CHECK-64-NEXT: stwx 6, 7, 4 312; CHECK-64-NEXT: addi 4, 1, -32 313; CHECK-64-NEXT: lxv 0, -16(1) 314; CHECK-64-NEXT: lwz 3, 1(3) 315; CHECK-64-NEXT: stxv 0, -32(1) 316; CHECK-64-NEXT: stwx 3, 4, 5 317; CHECK-64-NEXT: lxv 34, -32(1) 318; CHECK-64-NEXT: blr 319; 320; CHECK-32-LABEL: testFloat2: 321; CHECK-32: # %bb.0: # %entry 322; CHECK-32-NEXT: lwz 6, 0(3) 323; CHECK-32-NEXT: addi 7, 1, -16 324; CHECK-32-NEXT: rlwinm 4, 4, 2, 28, 29 325; CHECK-32-NEXT: stxv 34, -16(1) 326; CHECK-32-NEXT: rlwinm 5, 5, 2, 28, 29 327; CHECK-32-NEXT: stwx 6, 7, 4 328; CHECK-32-NEXT: addi 4, 1, -48 329; CHECK-32-NEXT: lxv 0, -16(1) 330; CHECK-32-NEXT: lwz 3, 1(3) 331; CHECK-32-NEXT: stxv 0, -48(1) 332; CHECK-32-NEXT: stwx 3, 4, 5 333; CHECK-32-NEXT: lxv 34, -48(1) 334; CHECK-32-NEXT: blr 335; 336; CHECK-64-P10-LABEL: testFloat2: 337; CHECK-64-P10: # %bb.0: # %entry 338; CHECK-64-P10-NEXT: lwz 6, 0(3) 339; CHECK-64-P10-NEXT: lwz 3, 1(3) 340; CHECK-64-P10-NEXT: slwi 4, 4, 2 341; CHECK-64-P10-NEXT: vinswlx 2, 4, 6 342; CHECK-64-P10-NEXT: slwi 4, 5, 2 343; CHECK-64-P10-NEXT: vinswlx 2, 4, 3 344; CHECK-64-P10-NEXT: blr 345; 346; CHECK-32-P10-LABEL: testFloat2: 347; CHECK-32-P10: # %bb.0: # %entry 348; CHECK-32-P10-NEXT: lwz 6, 0(3) 349; CHECK-32-P10-NEXT: lwz 3, 1(3) 350; CHECK-32-P10-NEXT: slwi 4, 4, 2 351; CHECK-32-P10-NEXT: vinswlx 2, 4, 6 352; CHECK-32-P10-NEXT: slwi 4, 5, 2 353; CHECK-32-P10-NEXT: vinswlx 2, 4, 3 354; CHECK-32-P10-NEXT: blr 355entry: 356 %add.ptr1 = getelementptr inbounds i8, ptr %b, i64 1 357 %0 = load float, ptr %b, align 4 358 %vecins = insertelement <4 x float> %a, float %0, i32 %idx1 359 %1 = load float, ptr %add.ptr1, align 4 360 %vecins2 = insertelement <4 x float> %vecins, float %1, i32 %idx2 361 ret <4 x float> %vecins2 362} 363 364define <4 x float> @testFloat3(<4 x float> %a, ptr %b, i32 zeroext %idx1, i32 zeroext %idx2) { 365; CHECK-64-LABEL: testFloat3: 366; CHECK-64: # %bb.0: # %entry 367; CHECK-64-NEXT: lis 6, 1 368; CHECK-64-NEXT: addi 7, 1, -16 369; CHECK-64-NEXT: rlwinm 4, 4, 2, 28, 29 370; CHECK-64-NEXT: rlwinm 5, 5, 2, 28, 29 371; CHECK-64-NEXT: lwzx 6, 3, 6 372; CHECK-64-NEXT: stxv 34, -16(1) 373; CHECK-64-NEXT: stwx 6, 7, 4 374; CHECK-64-NEXT: li 4, 1 375; CHECK-64-NEXT: lxv 0, -16(1) 376; CHECK-64-NEXT: rldic 4, 4, 36, 27 377; CHECK-64-NEXT: lwzx 3, 3, 4 378; CHECK-64-NEXT: addi 4, 1, -32 379; CHECK-64-NEXT: stxv 0, -32(1) 380; CHECK-64-NEXT: stwx 3, 4, 5 381; CHECK-64-NEXT: lxv 34, -32(1) 382; CHECK-64-NEXT: blr 383; 384; CHECK-32-LABEL: testFloat3: 385; CHECK-32: # %bb.0: # %entry 386; CHECK-32-NEXT: lis 6, 1 387; CHECK-32-NEXT: addi 7, 1, -16 388; CHECK-32-NEXT: rlwinm 4, 4, 2, 28, 29 389; CHECK-32-NEXT: rlwinm 5, 5, 2, 28, 29 390; CHECK-32-NEXT: lwzx 6, 3, 6 391; CHECK-32-NEXT: stxv 34, -16(1) 392; CHECK-32-NEXT: stwx 6, 7, 4 393; CHECK-32-NEXT: addi 4, 1, -48 394; CHECK-32-NEXT: lxv 0, -16(1) 395; CHECK-32-NEXT: lwz 3, 0(3) 396; CHECK-32-NEXT: stxv 0, -48(1) 397; CHECK-32-NEXT: stwx 3, 4, 5 398; CHECK-32-NEXT: lxv 34, -48(1) 399; CHECK-32-NEXT: blr 400; 401; CHECK-64-P10-LABEL: testFloat3: 402; CHECK-64-P10: # %bb.0: # %entry 403; CHECK-64-P10-NEXT: plwz 6, 65536(3), 0 404; CHECK-64-P10-NEXT: slwi 4, 4, 2 405; CHECK-64-P10-NEXT: vinswlx 2, 4, 6 406; CHECK-64-P10-NEXT: li 4, 1 407; CHECK-64-P10-NEXT: rldic 4, 4, 36, 27 408; CHECK-64-P10-NEXT: lwzx 3, 3, 4 409; CHECK-64-P10-NEXT: slwi 4, 5, 2 410; CHECK-64-P10-NEXT: vinswlx 2, 4, 3 411; CHECK-64-P10-NEXT: blr 412; 413; CHECK-32-P10-LABEL: testFloat3: 414; CHECK-32-P10: # %bb.0: # %entry 415; CHECK-32-P10-NEXT: plwz 6, 65536(3), 0 416; CHECK-32-P10-NEXT: lwz 3, 0(3) 417; CHECK-32-P10-NEXT: slwi 4, 4, 2 418; CHECK-32-P10-NEXT: vinswlx 2, 4, 6 419; CHECK-32-P10-NEXT: slwi 4, 5, 2 420; CHECK-32-P10-NEXT: vinswlx 2, 4, 3 421; CHECK-32-P10-NEXT: blr 422entry: 423 %add.ptr = getelementptr inbounds i8, ptr %b, i64 65536 424 %add.ptr1 = getelementptr inbounds i8, ptr %b, i64 68719476736 425 %0 = load float, ptr %add.ptr, align 4 426 %vecins = insertelement <4 x float> %a, float %0, i32 %idx1 427 %1 = load float, ptr %add.ptr1, align 4 428 %vecins2 = insertelement <4 x float> %vecins, float %1, i32 %idx2 429 ret <4 x float> %vecins2 430} 431 432; Float immediate 433 434define <4 x float> @testFloatImm1(<4 x float> %a, float %b) { 435; CHECK-64-LABEL: testFloatImm1: 436; CHECK-64: # %bb.0: # %entry 437; CHECK-64-NEXT: xscvdpspn 0, 1 438; CHECK-64-NEXT: xxinsertw 34, 0, 0 439; CHECK-64-NEXT: xxinsertw 34, 0, 8 440; CHECK-64-NEXT: blr 441; 442; CHECK-32-LABEL: testFloatImm1: 443; CHECK-32: # %bb.0: # %entry 444; CHECK-32-NEXT: xscvdpspn 0, 1 445; CHECK-32-NEXT: xxinsertw 34, 0, 0 446; CHECK-32-NEXT: xxinsertw 34, 0, 8 447; CHECK-32-NEXT: blr 448; 449; CHECK-64-P10-LABEL: testFloatImm1: 450; CHECK-64-P10: # %bb.0: # %entry 451; CHECK-64-P10-NEXT: xscvdpspn 0, 1 452; CHECK-64-P10-NEXT: xxinsertw 34, 0, 0 453; CHECK-64-P10-NEXT: xxinsertw 34, 0, 8 454; CHECK-64-P10-NEXT: blr 455; 456; CHECK-32-P10-LABEL: testFloatImm1: 457; CHECK-32-P10: # %bb.0: # %entry 458; CHECK-32-P10-NEXT: xscvdpspn 0, 1 459; CHECK-32-P10-NEXT: xxinsertw 34, 0, 0 460; CHECK-32-P10-NEXT: xxinsertw 34, 0, 8 461; CHECK-32-P10-NEXT: blr 462entry: 463 %vecins = insertelement <4 x float> %a, float %b, i32 0 464 %vecins1 = insertelement <4 x float> %vecins, float %b, i32 2 465 ret <4 x float> %vecins1 466} 467 468define <4 x float> @testFloatImm2(<4 x float> %a, ptr %b) { 469; CHECK-64-LABEL: testFloatImm2: 470; CHECK-64: # %bb.0: # %entry 471; CHECK-64-NEXT: lwz 4, 0(3) 472; CHECK-64-NEXT: lwz 3, 4(3) 473; CHECK-64-NEXT: mtfprwz 0, 4 474; CHECK-64-NEXT: xxinsertw 34, 0, 0 475; CHECK-64-NEXT: mtfprwz 0, 3 476; CHECK-64-NEXT: xxinsertw 34, 0, 8 477; CHECK-64-NEXT: blr 478; 479; CHECK-32-LABEL: testFloatImm2: 480; CHECK-32: # %bb.0: # %entry 481; CHECK-32-NEXT: lwz 4, 0(3) 482; CHECK-32-NEXT: lwz 3, 4(3) 483; CHECK-32-NEXT: mtfprwz 0, 4 484; CHECK-32-NEXT: xxinsertw 34, 0, 0 485; CHECK-32-NEXT: mtfprwz 0, 3 486; CHECK-32-NEXT: xxinsertw 34, 0, 8 487; CHECK-32-NEXT: blr 488; 489; CHECK-64-P10-LABEL: testFloatImm2: 490; CHECK-64-P10: # %bb.0: # %entry 491; CHECK-64-P10-NEXT: lwz 4, 0(3) 492; CHECK-64-P10-NEXT: lwz 3, 4(3) 493; CHECK-64-P10-NEXT: vinsw 2, 4, 0 494; CHECK-64-P10-NEXT: vinsw 2, 3, 8 495; CHECK-64-P10-NEXT: blr 496; 497; CHECK-32-P10-LABEL: testFloatImm2: 498; CHECK-32-P10: # %bb.0: # %entry 499; CHECK-32-P10-NEXT: lwz 4, 0(3) 500; CHECK-32-P10-NEXT: lwz 3, 4(3) 501; CHECK-32-P10-NEXT: vinsw 2, 4, 0 502; CHECK-32-P10-NEXT: vinsw 2, 3, 8 503; CHECK-32-P10-NEXT: blr 504entry: 505 %add.ptr1 = getelementptr inbounds i32, ptr %b, i64 1 506 %0 = load float, ptr %b, align 4 507 %vecins = insertelement <4 x float> %a, float %0, i32 0 508 %1 = load float, ptr %add.ptr1, align 4 509 %vecins2 = insertelement <4 x float> %vecins, float %1, i32 2 510 ret <4 x float> %vecins2 511} 512 513define <4 x float> @testFloatImm3(<4 x float> %a, ptr %b) { 514; CHECK-64-LABEL: testFloatImm3: 515; CHECK-64: # %bb.0: # %entry 516; CHECK-64-NEXT: lis 4, 4 517; CHECK-64-NEXT: lwzx 4, 3, 4 518; CHECK-64-NEXT: mtfprwz 0, 4 519; CHECK-64-NEXT: li 4, 1 520; CHECK-64-NEXT: rldic 4, 4, 38, 25 521; CHECK-64-NEXT: xxinsertw 34, 0, 0 522; CHECK-64-NEXT: lwzx 3, 3, 4 523; CHECK-64-NEXT: mtfprwz 0, 3 524; CHECK-64-NEXT: xxinsertw 34, 0, 8 525; CHECK-64-NEXT: blr 526; 527; CHECK-32-LABEL: testFloatImm3: 528; CHECK-32: # %bb.0: # %entry 529; CHECK-32-NEXT: lis 4, 4 530; CHECK-32-NEXT: lwzx 4, 3, 4 531; CHECK-32-NEXT: lwz 3, 0(3) 532; CHECK-32-NEXT: mtfprwz 0, 4 533; CHECK-32-NEXT: xxinsertw 34, 0, 0 534; CHECK-32-NEXT: mtfprwz 0, 3 535; CHECK-32-NEXT: xxinsertw 34, 0, 8 536; CHECK-32-NEXT: blr 537; 538; CHECK-64-P10-LABEL: testFloatImm3: 539; CHECK-64-P10: # %bb.0: # %entry 540; CHECK-64-P10-NEXT: plwz 4, 262144(3), 0 541; CHECK-64-P10-NEXT: vinsw 2, 4, 0 542; CHECK-64-P10-NEXT: li 4, 1 543; CHECK-64-P10-NEXT: rldic 4, 4, 38, 25 544; CHECK-64-P10-NEXT: lwzx 3, 3, 4 545; CHECK-64-P10-NEXT: vinsw 2, 3, 8 546; CHECK-64-P10-NEXT: blr 547; 548; CHECK-32-P10-LABEL: testFloatImm3: 549; CHECK-32-P10: # %bb.0: # %entry 550; CHECK-32-P10-NEXT: plwz 4, 262144(3), 0 551; CHECK-32-P10-NEXT: lwz 3, 0(3) 552; CHECK-32-P10-NEXT: vinsw 2, 4, 0 553; CHECK-32-P10-NEXT: vinsw 2, 3, 8 554; CHECK-32-P10-NEXT: blr 555entry: 556 %add.ptr = getelementptr inbounds i32, ptr %b, i64 65536 557 %add.ptr1 = getelementptr inbounds i32, ptr %b, i64 68719476736 558 %0 = load float, ptr %add.ptr, align 4 559 %vecins = insertelement <4 x float> %a, float %0, i32 0 560 %1 = load float, ptr %add.ptr1, align 4 561 %vecins2 = insertelement <4 x float> %vecins, float %1, i32 2 562 ret <4 x float> %vecins2 563} 564 565; Double indexed 566 567define <2 x double> @testDouble1(<2 x double> %a, double %b, i32 zeroext %idx1) { 568; CHECK-64-LABEL: testDouble1: 569; CHECK-64: # %bb.0: # %entry 570; CHECK-64-NEXT: rlwinm 3, 4, 3, 28, 28 571; CHECK-64-NEXT: addi 4, 1, -16 572; CHECK-64-NEXT: stxv 34, -16(1) 573; CHECK-64-NEXT: stfdx 1, 4, 3 574; CHECK-64-NEXT: lxv 34, -16(1) 575; CHECK-64-NEXT: blr 576; 577; CHECK-32-LABEL: testDouble1: 578; CHECK-32: # %bb.0: # %entry 579; CHECK-32-NEXT: addi 4, 1, -16 580; CHECK-32-NEXT: rlwinm 3, 5, 3, 28, 28 581; CHECK-32-NEXT: stxv 34, -16(1) 582; CHECK-32-NEXT: stfdx 1, 4, 3 583; CHECK-32-NEXT: lxv 34, -16(1) 584; CHECK-32-NEXT: blr 585; 586; CHECK-64-P10-LABEL: testDouble1: 587; CHECK-64-P10: # %bb.0: # %entry 588; CHECK-64-P10-NEXT: mffprd 3, 1 589; CHECK-64-P10-NEXT: rlwinm 4, 4, 3, 0, 28 590; CHECK-64-P10-NEXT: vinsdlx 2, 4, 3 591; CHECK-64-P10-NEXT: blr 592; 593; CHECK-32-P10-LABEL: testDouble1: 594; CHECK-32-P10: # %bb.0: # %entry 595; CHECK-32-P10-NEXT: addi 4, 1, -16 596; CHECK-32-P10-NEXT: rlwinm 3, 5, 3, 28, 28 597; CHECK-32-P10-NEXT: stxv 34, -16(1) 598; CHECK-32-P10-NEXT: stfdx 1, 4, 3 599; CHECK-32-P10-NEXT: lxv 34, -16(1) 600; CHECK-32-P10-NEXT: blr 601entry: 602 %vecins = insertelement <2 x double> %a, double %b, i32 %idx1 603 ret <2 x double> %vecins 604} 605 606define <2 x double> @testDouble2(<2 x double> %a, ptr %b, i32 zeroext %idx1, i32 zeroext %idx2) { 607; CHECK-64-LABEL: testDouble2: 608; CHECK-64: # %bb.0: # %entry 609; CHECK-64-NEXT: ld 6, 0(3) 610; CHECK-64-NEXT: addi 7, 1, -32 611; CHECK-64-NEXT: rlwinm 4, 4, 3, 28, 28 612; CHECK-64-NEXT: stxv 34, -32(1) 613; CHECK-64-NEXT: rlwinm 5, 5, 3, 28, 28 614; CHECK-64-NEXT: stdx 6, 7, 4 615; CHECK-64-NEXT: li 4, 1 616; CHECK-64-NEXT: lxv 0, -32(1) 617; CHECK-64-NEXT: ldx 3, 3, 4 618; CHECK-64-NEXT: addi 4, 1, -16 619; CHECK-64-NEXT: stxv 0, -16(1) 620; CHECK-64-NEXT: stdx 3, 4, 5 621; CHECK-64-NEXT: lxv 34, -16(1) 622; CHECK-64-NEXT: blr 623; 624; CHECK-32-LABEL: testDouble2: 625; CHECK-32: # %bb.0: # %entry 626; CHECK-32-NEXT: lfd 0, 0(3) 627; CHECK-32-NEXT: addi 6, 1, -32 628; CHECK-32-NEXT: rlwinm 4, 4, 3, 28, 28 629; CHECK-32-NEXT: stxv 34, -32(1) 630; CHECK-32-NEXT: rlwinm 5, 5, 3, 28, 28 631; CHECK-32-NEXT: stfdx 0, 6, 4 632; CHECK-32-NEXT: lxv 0, -32(1) 633; CHECK-32-NEXT: lfd 1, 1(3) 634; CHECK-32-NEXT: addi 3, 1, -16 635; CHECK-32-NEXT: stxv 0, -16(1) 636; CHECK-32-NEXT: stfdx 1, 3, 5 637; CHECK-32-NEXT: lxv 34, -16(1) 638; CHECK-32-NEXT: blr 639; 640; CHECK-64-P10-LABEL: testDouble2: 641; CHECK-64-P10: # %bb.0: # %entry 642; CHECK-64-P10-NEXT: ld 6, 0(3) 643; CHECK-64-P10-NEXT: pld 3, 1(3), 0 644; CHECK-64-P10-NEXT: rlwinm 4, 4, 3, 0, 28 645; CHECK-64-P10-NEXT: vinsdlx 2, 4, 6 646; CHECK-64-P10-NEXT: rlwinm 4, 5, 3, 0, 28 647; CHECK-64-P10-NEXT: vinsdlx 2, 4, 3 648; CHECK-64-P10-NEXT: blr 649; 650; CHECK-32-P10-LABEL: testDouble2: 651; CHECK-32-P10: # %bb.0: # %entry 652; CHECK-32-P10-NEXT: lfd 0, 0(3) 653; CHECK-32-P10-NEXT: addi 6, 1, -32 654; CHECK-32-P10-NEXT: rlwinm 4, 4, 3, 28, 28 655; CHECK-32-P10-NEXT: stxv 34, -32(1) 656; CHECK-32-P10-NEXT: rlwinm 5, 5, 3, 28, 28 657; CHECK-32-P10-NEXT: stfdx 0, 6, 4 658; CHECK-32-P10-NEXT: lxv 0, -32(1) 659; CHECK-32-P10-NEXT: plfd 1, 1(3), 0 660; CHECK-32-P10-NEXT: addi 3, 1, -16 661; CHECK-32-P10-NEXT: stxv 0, -16(1) 662; CHECK-32-P10-NEXT: stfdx 1, 3, 5 663; CHECK-32-P10-NEXT: lxv 34, -16(1) 664; CHECK-32-P10-NEXT: blr 665entry: 666 %add.ptr1 = getelementptr inbounds i8, ptr %b, i64 1 667 %0 = load double, ptr %b, align 8 668 %vecins = insertelement <2 x double> %a, double %0, i32 %idx1 669 %1 = load double, ptr %add.ptr1, align 8 670 %vecins2 = insertelement <2 x double> %vecins, double %1, i32 %idx2 671 ret <2 x double> %vecins2 672} 673 674define <2 x double> @testDouble3(<2 x double> %a, ptr %b, i32 zeroext %idx1, i32 zeroext %idx2) { 675; CHECK-64-LABEL: testDouble3: 676; CHECK-64: # %bb.0: # %entry 677; CHECK-64-NEXT: lis 6, 1 678; CHECK-64-NEXT: addi 7, 1, -32 679; CHECK-64-NEXT: rlwinm 4, 4, 3, 28, 28 680; CHECK-64-NEXT: rlwinm 5, 5, 3, 28, 28 681; CHECK-64-NEXT: ldx 6, 3, 6 682; CHECK-64-NEXT: stxv 34, -32(1) 683; CHECK-64-NEXT: stdx 6, 7, 4 684; CHECK-64-NEXT: li 4, 1 685; CHECK-64-NEXT: lxv 0, -32(1) 686; CHECK-64-NEXT: rldic 4, 4, 36, 27 687; CHECK-64-NEXT: ldx 3, 3, 4 688; CHECK-64-NEXT: addi 4, 1, -16 689; CHECK-64-NEXT: stxv 0, -16(1) 690; CHECK-64-NEXT: stdx 3, 4, 5 691; CHECK-64-NEXT: lxv 34, -16(1) 692; CHECK-64-NEXT: blr 693; 694; CHECK-32-LABEL: testDouble3: 695; CHECK-32: # %bb.0: # %entry 696; CHECK-32-NEXT: lis 6, 1 697; CHECK-32-NEXT: rlwinm 4, 4, 3, 28, 28 698; CHECK-32-NEXT: rlwinm 5, 5, 3, 28, 28 699; CHECK-32-NEXT: lfdx 0, 3, 6 700; CHECK-32-NEXT: addi 6, 1, -32 701; CHECK-32-NEXT: stxv 34, -32(1) 702; CHECK-32-NEXT: stfdx 0, 6, 4 703; CHECK-32-NEXT: lxv 0, -32(1) 704; CHECK-32-NEXT: lfd 1, 0(3) 705; CHECK-32-NEXT: addi 3, 1, -16 706; CHECK-32-NEXT: stxv 0, -16(1) 707; CHECK-32-NEXT: stfdx 1, 3, 5 708; CHECK-32-NEXT: lxv 34, -16(1) 709; CHECK-32-NEXT: blr 710; 711; CHECK-64-P10-LABEL: testDouble3: 712; CHECK-64-P10: # %bb.0: # %entry 713; CHECK-64-P10-NEXT: pld 6, 65536(3), 0 714; CHECK-64-P10-NEXT: rlwinm 4, 4, 3, 0, 28 715; CHECK-64-P10-NEXT: vinsdlx 2, 4, 6 716; CHECK-64-P10-NEXT: li 4, 1 717; CHECK-64-P10-NEXT: rldic 4, 4, 36, 27 718; CHECK-64-P10-NEXT: ldx 3, 3, 4 719; CHECK-64-P10-NEXT: rlwinm 4, 5, 3, 0, 28 720; CHECK-64-P10-NEXT: vinsdlx 2, 4, 3 721; CHECK-64-P10-NEXT: blr 722; 723; CHECK-32-P10-LABEL: testDouble3: 724; CHECK-32-P10: # %bb.0: # %entry 725; CHECK-32-P10-NEXT: plfd 0, 65536(3), 0 726; CHECK-32-P10-NEXT: addi 6, 1, -32 727; CHECK-32-P10-NEXT: rlwinm 4, 4, 3, 28, 28 728; CHECK-32-P10-NEXT: stxv 34, -32(1) 729; CHECK-32-P10-NEXT: rlwinm 5, 5, 3, 28, 28 730; CHECK-32-P10-NEXT: stfdx 0, 6, 4 731; CHECK-32-P10-NEXT: lxv 0, -32(1) 732; CHECK-32-P10-NEXT: lfd 1, 0(3) 733; CHECK-32-P10-NEXT: addi 3, 1, -16 734; CHECK-32-P10-NEXT: stxv 0, -16(1) 735; CHECK-32-P10-NEXT: stfdx 1, 3, 5 736; CHECK-32-P10-NEXT: lxv 34, -16(1) 737; CHECK-32-P10-NEXT: blr 738entry: 739 %add.ptr = getelementptr inbounds i8, ptr %b, i64 65536 740 %add.ptr1 = getelementptr inbounds i8, ptr %b, i64 68719476736 741 %0 = load double, ptr %add.ptr, align 8 742 %vecins = insertelement <2 x double> %a, double %0, i32 %idx1 743 %1 = load double, ptr %add.ptr1, align 8 744 %vecins2 = insertelement <2 x double> %vecins, double %1, i32 %idx2 745 ret <2 x double> %vecins2 746} 747 748; Double immediate 749 750define <2 x double> @testDoubleImm1(<2 x double> %a, double %b) { 751; CHECK-64-LABEL: testDoubleImm1: 752; CHECK-64: # %bb.0: # %entry 753; CHECK-64-NEXT: xxpermdi 34, 1, 34, 1 754; CHECK-64-NEXT: blr 755; 756; CHECK-32-LABEL: testDoubleImm1: 757; CHECK-32: # %bb.0: # %entry 758; CHECK-32-NEXT: xxpermdi 34, 1, 34, 1 759; CHECK-32-NEXT: blr 760; 761; CHECK-64-P10-LABEL: testDoubleImm1: 762; CHECK-64-P10: # %bb.0: # %entry 763; CHECK-64-P10-NEXT: xxpermdi 34, 1, 34, 1 764; CHECK-64-P10-NEXT: blr 765; 766; CHECK-32-P10-LABEL: testDoubleImm1: 767; CHECK-32-P10: # %bb.0: # %entry 768; CHECK-32-P10-NEXT: xxpermdi 34, 1, 34, 1 769; CHECK-32-P10-NEXT: blr 770entry: 771 %vecins = insertelement <2 x double> %a, double %b, i32 0 772 ret <2 x double> %vecins 773} 774 775define <2 x double> @testDoubleImm2(<2 x double> %a, ptr %b) { 776; CHECK-64-LABEL: testDoubleImm2: 777; CHECK-64: # %bb.0: # %entry 778; CHECK-64-NEXT: lfd 0, 0(3) 779; CHECK-64-NEXT: xxpermdi 34, 0, 34, 1 780; CHECK-64-NEXT: blr 781; 782; CHECK-32-LABEL: testDoubleImm2: 783; CHECK-32: # %bb.0: # %entry 784; CHECK-32-NEXT: lfd 0, 0(3) 785; CHECK-32-NEXT: xxpermdi 34, 0, 34, 1 786; CHECK-32-NEXT: blr 787; 788; CHECK-64-P10-LABEL: testDoubleImm2: 789; CHECK-64-P10: # %bb.0: # %entry 790; CHECK-64-P10-NEXT: lfd 0, 0(3) 791; CHECK-64-P10-NEXT: xxpermdi 34, 0, 34, 1 792; CHECK-64-P10-NEXT: blr 793; 794; CHECK-32-P10-LABEL: testDoubleImm2: 795; CHECK-32-P10: # %bb.0: # %entry 796; CHECK-32-P10-NEXT: lfd 0, 0(3) 797; CHECK-32-P10-NEXT: xxpermdi 34, 0, 34, 1 798; CHECK-32-P10-NEXT: blr 799entry: 800 %0 = load double, ptr %b, align 8 801 %vecins = insertelement <2 x double> %a, double %0, i32 0 802 ret <2 x double> %vecins 803} 804 805define <2 x double> @testDoubleImm3(<2 x double> %a, ptr %b) { 806; CHECK-64-LABEL: testDoubleImm3: 807; CHECK-64: # %bb.0: # %entry 808; CHECK-64-NEXT: lfd 0, 4(3) 809; CHECK-64-NEXT: xxpermdi 34, 0, 34, 1 810; CHECK-64-NEXT: blr 811; 812; CHECK-32-LABEL: testDoubleImm3: 813; CHECK-32: # %bb.0: # %entry 814; CHECK-32-NEXT: lfd 0, 4(3) 815; CHECK-32-NEXT: xxpermdi 34, 0, 34, 1 816; CHECK-32-NEXT: blr 817; 818; CHECK-64-P10-LABEL: testDoubleImm3: 819; CHECK-64-P10: # %bb.0: # %entry 820; CHECK-64-P10-NEXT: lfd 0, 4(3) 821; CHECK-64-P10-NEXT: xxpermdi 34, 0, 34, 1 822; CHECK-64-P10-NEXT: blr 823; 824; CHECK-32-P10-LABEL: testDoubleImm3: 825; CHECK-32-P10: # %bb.0: # %entry 826; CHECK-32-P10-NEXT: lfd 0, 4(3) 827; CHECK-32-P10-NEXT: xxpermdi 34, 0, 34, 1 828; CHECK-32-P10-NEXT: blr 829entry: 830 %add.ptr = getelementptr inbounds i32, ptr %b, i64 1 831 %0 = load double, ptr %add.ptr, align 8 832 %vecins = insertelement <2 x double> %a, double %0, i32 0 833 ret <2 x double> %vecins 834} 835 836define <2 x double> @testDoubleImm4(<2 x double> %a, ptr %b) { 837; CHECK-64-LABEL: testDoubleImm4: 838; CHECK-64: # %bb.0: # %entry 839; CHECK-64-NEXT: lis 4, 4 840; CHECK-64-NEXT: lfdx 0, 3, 4 841; CHECK-64-NEXT: xxpermdi 34, 0, 34, 1 842; CHECK-64-NEXT: blr 843; 844; CHECK-32-LABEL: testDoubleImm4: 845; CHECK-32: # %bb.0: # %entry 846; CHECK-32-NEXT: lis 4, 4 847; CHECK-32-NEXT: lfdx 0, 3, 4 848; CHECK-32-NEXT: xxpermdi 34, 0, 34, 1 849; CHECK-32-NEXT: blr 850; 851; CHECK-64-P10-LABEL: testDoubleImm4: 852; CHECK-64-P10: # %bb.0: # %entry 853; CHECK-64-P10-NEXT: plfd 0, 262144(3), 0 854; CHECK-64-P10-NEXT: xxpermdi 34, 0, 34, 1 855; CHECK-64-P10-NEXT: blr 856; 857; CHECK-32-P10-LABEL: testDoubleImm4: 858; CHECK-32-P10: # %bb.0: # %entry 859; CHECK-32-P10-NEXT: plfd 0, 262144(3), 0 860; CHECK-32-P10-NEXT: xxpermdi 34, 0, 34, 1 861; CHECK-32-P10-NEXT: blr 862entry: 863 %add.ptr = getelementptr inbounds i32, ptr %b, i64 65536 864 %0 = load double, ptr %add.ptr, align 8 865 %vecins = insertelement <2 x double> %a, double %0, i32 0 866 ret <2 x double> %vecins 867} 868 869define <2 x double> @testDoubleImm5(<2 x double> %a, ptr %b) { 870; CHECK-64-LABEL: testDoubleImm5: 871; CHECK-64: # %bb.0: # %entry 872; CHECK-64-NEXT: li 4, 1 873; CHECK-64-NEXT: rldic 4, 4, 38, 25 874; CHECK-64-NEXT: lfdx 0, 3, 4 875; CHECK-64-NEXT: xxpermdi 34, 0, 34, 1 876; CHECK-64-NEXT: blr 877; 878; CHECK-32-LABEL: testDoubleImm5: 879; CHECK-32: # %bb.0: # %entry 880; CHECK-32-NEXT: lfd 0, 0(3) 881; CHECK-32-NEXT: xxpermdi 34, 0, 34, 1 882; CHECK-32-NEXT: blr 883; 884; CHECK-64-P10-LABEL: testDoubleImm5: 885; CHECK-64-P10: # %bb.0: # %entry 886; CHECK-64-P10-NEXT: li 4, 1 887; CHECK-64-P10-NEXT: rldic 4, 4, 38, 25 888; CHECK-64-P10-NEXT: lfdx 0, 3, 4 889; CHECK-64-P10-NEXT: xxpermdi 34, 0, 34, 1 890; CHECK-64-P10-NEXT: blr 891; 892; CHECK-32-P10-LABEL: testDoubleImm5: 893; CHECK-32-P10: # %bb.0: # %entry 894; CHECK-32-P10-NEXT: lfd 0, 0(3) 895; CHECK-32-P10-NEXT: xxpermdi 34, 0, 34, 1 896; CHECK-32-P10-NEXT: blr 897entry: 898 %add.ptr = getelementptr inbounds i32, ptr %b, i64 68719476736 899 %0 = load double, ptr %add.ptr, align 8 900 %vecins = insertelement <2 x double> %a, double %0, i32 0 901 ret <2 x double> %vecins 902} 903 904