xref: /llvm-project/llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll (revision 934d5fa2b8672695c335deed0e19d0e777c98403) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \
3; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-64
4; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff \
5; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-32
6
7define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
8; CHECK-64-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_:
9; CHECK-64:       # %bb.0: # %entry
10; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
11; CHECK-64-NEXT:    xxinsertw 34, 0, 0
12; CHECK-64-NEXT:    blr
13;
14; CHECK-32-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_:
15; CHECK-32:       # %bb.0: # %entry
16; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
17; CHECK-32-NEXT:    xxinsertw 34, 0, 0
18; CHECK-32-NEXT:    blr
19entry:
20  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
21  ret <4 x float> %vecins
22}
23
24define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
25; CHECK-64-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_:
26; CHECK-64:       # %bb.0: # %entry
27; CHECK-64-NEXT:    xxinsertw 34, 35, 0
28; CHECK-64-NEXT:    blr
29;
30; CHECK-32-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_:
31; CHECK-32:       # %bb.0: # %entry
32; CHECK-32-NEXT:    xxinsertw 34, 35, 0
33; CHECK-32-NEXT:    blr
34entry:
35  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
36  ret <4 x float> %vecins
37}
38
39define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
40; CHECK-64-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_:
41; CHECK-64:       # %bb.0: # %entry
42; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
43; CHECK-64-NEXT:    xxinsertw 34, 0, 0
44; CHECK-64-NEXT:    blr
45;
46; CHECK-32-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_:
47; CHECK-32:       # %bb.0: # %entry
48; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
49; CHECK-32-NEXT:    xxinsertw 34, 0, 0
50; CHECK-32-NEXT:    blr
51entry:
52  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
53  ret <4 x float> %vecins
54}
55
56define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
57; CHECK-64-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_:
58; CHECK-64:       # %bb.0: # %entry
59; CHECK-64-NEXT:    xxswapd 0, 35
60; CHECK-64-NEXT:    xxinsertw 34, 0, 0
61; CHECK-64-NEXT:    blr
62;
63; CHECK-32-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_:
64; CHECK-32:       # %bb.0: # %entry
65; CHECK-32-NEXT:    xxswapd 0, 35
66; CHECK-32-NEXT:    xxinsertw 34, 0, 0
67; CHECK-32-NEXT:    blr
68entry:
69  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>
70  ret <4 x float> %vecins
71}
72
73define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
74; CHECK-64-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_:
75; CHECK-64:       # %bb.0: # %entry
76; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
77; CHECK-64-NEXT:    xxinsertw 34, 0, 4
78; CHECK-64-NEXT:    blr
79;
80; CHECK-32-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_:
81; CHECK-32:       # %bb.0: # %entry
82; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
83; CHECK-32-NEXT:    xxinsertw 34, 0, 4
84; CHECK-32-NEXT:    blr
85entry:
86  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
87  ret <4 x float> %vecins
88}
89
90define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
91; CHECK-64-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_:
92; CHECK-64:       # %bb.0: # %entry
93; CHECK-64-NEXT:    xxinsertw 34, 35, 4
94; CHECK-64-NEXT:    blr
95;
96; CHECK-32-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_:
97; CHECK-32:       # %bb.0: # %entry
98; CHECK-32-NEXT:    xxinsertw 34, 35, 4
99; CHECK-32-NEXT:    blr
100entry:
101  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
102  ret <4 x float> %vecins
103}
104
105define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
106; CHECK-64-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_:
107; CHECK-64:       # %bb.0: # %entry
108; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
109; CHECK-64-NEXT:    xxinsertw 34, 0, 4
110; CHECK-64-NEXT:    blr
111;
112; CHECK-32-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_:
113; CHECK-32:       # %bb.0: # %entry
114; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
115; CHECK-32-NEXT:    xxinsertw 34, 0, 4
116; CHECK-32-NEXT:    blr
117entry:
118  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
119  ret <4 x float> %vecins
120}
121
122define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
123; CHECK-64-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_:
124; CHECK-64:       # %bb.0: # %entry
125; CHECK-64-NEXT:    xxswapd 0, 35
126; CHECK-64-NEXT:    xxinsertw 34, 0, 4
127; CHECK-64-NEXT:    blr
128;
129; CHECK-32-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_:
130; CHECK-32:       # %bb.0: # %entry
131; CHECK-32-NEXT:    xxswapd 0, 35
132; CHECK-32-NEXT:    xxinsertw 34, 0, 4
133; CHECK-32-NEXT:    blr
134entry:
135  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
136  ret <4 x float> %vecins
137}
138
139define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
140; CHECK-64-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_:
141; CHECK-64:       # %bb.0: # %entry
142; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
143; CHECK-64-NEXT:    xxinsertw 34, 0, 8
144; CHECK-64-NEXT:    blr
145;
146; CHECK-32-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_:
147; CHECK-32:       # %bb.0: # %entry
148; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
149; CHECK-32-NEXT:    xxinsertw 34, 0, 8
150; CHECK-32-NEXT:    blr
151entry:
152  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
153  ret <4 x float> %vecins
154}
155
156define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
157; CHECK-64-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_:
158; CHECK-64:       # %bb.0: # %entry
159; CHECK-64-NEXT:    xxinsertw 34, 35, 8
160; CHECK-64-NEXT:    blr
161;
162; CHECK-32-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_:
163; CHECK-32:       # %bb.0: # %entry
164; CHECK-32-NEXT:    xxinsertw 34, 35, 8
165; CHECK-32-NEXT:    blr
166entry:
167  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
168  ret <4 x float> %vecins
169}
170
171define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
172; CHECK-64-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_:
173; CHECK-64:       # %bb.0: # %entry
174; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
175; CHECK-64-NEXT:    xxinsertw 34, 0, 8
176; CHECK-64-NEXT:    blr
177;
178; CHECK-32-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_:
179; CHECK-32:       # %bb.0: # %entry
180; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
181; CHECK-32-NEXT:    xxinsertw 34, 0, 8
182; CHECK-32-NEXT:    blr
183entry:
184  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
185  ret <4 x float> %vecins
186}
187
188define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
189; CHECK-64-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_:
190; CHECK-64:       # %bb.0: # %entry
191; CHECK-64-NEXT:    xxswapd 0, 35
192; CHECK-64-NEXT:    xxinsertw 34, 0, 8
193; CHECK-64-NEXT:    blr
194;
195; CHECK-32-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_:
196; CHECK-32:       # %bb.0: # %entry
197; CHECK-32-NEXT:    xxswapd 0, 35
198; CHECK-32-NEXT:    xxinsertw 34, 0, 8
199; CHECK-32-NEXT:    blr
200entry:
201  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>
202  ret <4 x float> %vecins
203}
204
205define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
206; CHECK-64-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_:
207; CHECK-64:       # %bb.0: # %entry
208; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
209; CHECK-64-NEXT:    xxinsertw 34, 0, 12
210; CHECK-64-NEXT:    blr
211;
212; CHECK-32-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_:
213; CHECK-32:       # %bb.0: # %entry
214; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
215; CHECK-32-NEXT:    xxinsertw 34, 0, 12
216; CHECK-32-NEXT:    blr
217entry:
218  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
219  ret <4 x float> %vecins
220}
221
222define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
223; CHECK-64-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_:
224; CHECK-64:       # %bb.0: # %entry
225; CHECK-64-NEXT:    xxinsertw 34, 35, 12
226; CHECK-64-NEXT:    blr
227;
228; CHECK-32-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_:
229; CHECK-32:       # %bb.0: # %entry
230; CHECK-32-NEXT:    xxinsertw 34, 35, 12
231; CHECK-32-NEXT:    blr
232entry:
233  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
234  ret <4 x float> %vecins
235}
236
237define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
238; CHECK-64-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_:
239; CHECK-64:       # %bb.0: # %entry
240; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
241; CHECK-64-NEXT:    xxinsertw 34, 0, 12
242; CHECK-64-NEXT:    blr
243;
244; CHECK-32-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_:
245; CHECK-32:       # %bb.0: # %entry
246; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
247; CHECK-32-NEXT:    xxinsertw 34, 0, 12
248; CHECK-32-NEXT:    blr
249entry:
250  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
251  ret <4 x float> %vecins
252}
253
254define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
255; CHECK-64-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_:
256; CHECK-64:       # %bb.0: # %entry
257; CHECK-64-NEXT:    xxswapd 0, 35
258; CHECK-64-NEXT:    xxinsertw 34, 0, 12
259; CHECK-64-NEXT:    blr
260;
261; CHECK-32-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_:
262; CHECK-32:       # %bb.0: # %entry
263; CHECK-32-NEXT:    xxswapd 0, 35
264; CHECK-32-NEXT:    xxinsertw 34, 0, 12
265; CHECK-32-NEXT:    blr
266entry:
267  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
268  ret <4 x float> %vecins
269}
270
271define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
272; CHECK-64-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_:
273; CHECK-64:       # %bb.0: # %entry
274; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
275; CHECK-64-NEXT:    xxinsertw 34, 0, 0
276; CHECK-64-NEXT:    blr
277;
278; CHECK-32-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_:
279; CHECK-32:       # %bb.0: # %entry
280; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
281; CHECK-32-NEXT:    xxinsertw 34, 0, 0
282; CHECK-32-NEXT:    blr
283entry:
284  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
285  ret <4 x i32> %vecins
286}
287
288define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
289; CHECK-64-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_:
290; CHECK-64:       # %bb.0: # %entry
291; CHECK-64-NEXT:    xxinsertw 34, 35, 0
292; CHECK-64-NEXT:    blr
293;
294; CHECK-32-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_:
295; CHECK-32:       # %bb.0: # %entry
296; CHECK-32-NEXT:    xxinsertw 34, 35, 0
297; CHECK-32-NEXT:    blr
298entry:
299  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
300  ret <4 x i32> %vecins
301}
302
303define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
304; CHECK-64-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_:
305; CHECK-64:       # %bb.0: # %entry
306; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
307; CHECK-64-NEXT:    xxinsertw 34, 0, 0
308; CHECK-64-NEXT:    blr
309;
310; CHECK-32-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_:
311; CHECK-32:       # %bb.0: # %entry
312; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
313; CHECK-32-NEXT:    xxinsertw 34, 0, 0
314; CHECK-32-NEXT:    blr
315entry:
316  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
317  ret <4 x i32> %vecins
318}
319
320define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
321; CHECK-64-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_:
322; CHECK-64:       # %bb.0: # %entry
323; CHECK-64-NEXT:    xxswapd 0, 35
324; CHECK-64-NEXT:    xxinsertw 34, 0, 0
325; CHECK-64-NEXT:    blr
326;
327; CHECK-32-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_:
328; CHECK-32:       # %bb.0: # %entry
329; CHECK-32-NEXT:    xxswapd 0, 35
330; CHECK-32-NEXT:    xxinsertw 34, 0, 0
331; CHECK-32-NEXT:    blr
332entry:
333  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>
334  ret <4 x i32> %vecins
335}
336
337define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
338; CHECK-64-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_:
339; CHECK-64:       # %bb.0: # %entry
340; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
341; CHECK-64-NEXT:    xxinsertw 34, 0, 4
342; CHECK-64-NEXT:    blr
343;
344; CHECK-32-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_:
345; CHECK-32:       # %bb.0: # %entry
346; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
347; CHECK-32-NEXT:    xxinsertw 34, 0, 4
348; CHECK-32-NEXT:    blr
349entry:
350  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
351  ret <4 x i32> %vecins
352}
353
354define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
355; CHECK-64-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_:
356; CHECK-64:       # %bb.0: # %entry
357; CHECK-64-NEXT:    xxinsertw 34, 35, 4
358; CHECK-64-NEXT:    blr
359;
360; CHECK-32-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_:
361; CHECK-32:       # %bb.0: # %entry
362; CHECK-32-NEXT:    xxinsertw 34, 35, 4
363; CHECK-32-NEXT:    blr
364entry:
365  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
366  ret <4 x i32> %vecins
367}
368
369define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
370; CHECK-64-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_:
371; CHECK-64:       # %bb.0: # %entry
372; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
373; CHECK-64-NEXT:    xxinsertw 34, 0, 4
374; CHECK-64-NEXT:    blr
375;
376; CHECK-32-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_:
377; CHECK-32:       # %bb.0: # %entry
378; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
379; CHECK-32-NEXT:    xxinsertw 34, 0, 4
380; CHECK-32-NEXT:    blr
381entry:
382  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
383  ret <4 x i32> %vecins
384}
385
386define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
387; CHECK-64-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_:
388; CHECK-64:       # %bb.0: # %entry
389; CHECK-64-NEXT:    xxswapd 0, 35
390; CHECK-64-NEXT:    xxinsertw 34, 0, 4
391; CHECK-64-NEXT:    blr
392;
393; CHECK-32-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_:
394; CHECK-32:       # %bb.0: # %entry
395; CHECK-32-NEXT:    xxswapd 0, 35
396; CHECK-32-NEXT:    xxinsertw 34, 0, 4
397; CHECK-32-NEXT:    blr
398entry:
399  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
400  ret <4 x i32> %vecins
401}
402
403define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
404; CHECK-64-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_:
405; CHECK-64:       # %bb.0: # %entry
406; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
407; CHECK-64-NEXT:    xxinsertw 34, 0, 8
408; CHECK-64-NEXT:    blr
409;
410; CHECK-32-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_:
411; CHECK-32:       # %bb.0: # %entry
412; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
413; CHECK-32-NEXT:    xxinsertw 34, 0, 8
414; CHECK-32-NEXT:    blr
415entry:
416  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
417  ret <4 x i32> %vecins
418}
419
420define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
421; CHECK-64-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_:
422; CHECK-64:       # %bb.0: # %entry
423; CHECK-64-NEXT:    xxinsertw 34, 35, 8
424; CHECK-64-NEXT:    blr
425;
426; CHECK-32-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_:
427; CHECK-32:       # %bb.0: # %entry
428; CHECK-32-NEXT:    xxinsertw 34, 35, 8
429; CHECK-32-NEXT:    blr
430entry:
431  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
432  ret <4 x i32> %vecins
433}
434
435define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
436; CHECK-64-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_:
437; CHECK-64:       # %bb.0: # %entry
438; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
439; CHECK-64-NEXT:    xxinsertw 34, 0, 8
440; CHECK-64-NEXT:    blr
441;
442; CHECK-32-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_:
443; CHECK-32:       # %bb.0: # %entry
444; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
445; CHECK-32-NEXT:    xxinsertw 34, 0, 8
446; CHECK-32-NEXT:    blr
447entry:
448  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
449  ret <4 x i32> %vecins
450}
451
452define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
453; CHECK-64-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_:
454; CHECK-64:       # %bb.0: # %entry
455; CHECK-64-NEXT:    xxswapd 0, 35
456; CHECK-64-NEXT:    xxinsertw 34, 0, 8
457; CHECK-64-NEXT:    blr
458;
459; CHECK-32-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_:
460; CHECK-32:       # %bb.0: # %entry
461; CHECK-32-NEXT:    xxswapd 0, 35
462; CHECK-32-NEXT:    xxinsertw 34, 0, 8
463; CHECK-32-NEXT:    blr
464entry:
465  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>
466  ret <4 x i32> %vecins
467}
468
469define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
470; CHECK-64-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_:
471; CHECK-64:       # %bb.0: # %entry
472; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
473; CHECK-64-NEXT:    xxinsertw 34, 0, 12
474; CHECK-64-NEXT:    blr
475;
476; CHECK-32-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_:
477; CHECK-32:       # %bb.0: # %entry
478; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
479; CHECK-32-NEXT:    xxinsertw 34, 0, 12
480; CHECK-32-NEXT:    blr
481entry:
482  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
483  ret <4 x i32> %vecins
484}
485
486define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
487; CHECK-64-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_:
488; CHECK-64:       # %bb.0: # %entry
489; CHECK-64-NEXT:    xxinsertw 34, 35, 12
490; CHECK-64-NEXT:    blr
491;
492; CHECK-32-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_:
493; CHECK-32:       # %bb.0: # %entry
494; CHECK-32-NEXT:    xxinsertw 34, 35, 12
495; CHECK-32-NEXT:    blr
496entry:
497  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
498  ret <4 x i32> %vecins
499}
500
501define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
502; CHECK-64-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_:
503; CHECK-64:       # %bb.0: # %entry
504; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
505; CHECK-64-NEXT:    xxinsertw 34, 0, 12
506; CHECK-64-NEXT:    blr
507;
508; CHECK-32-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_:
509; CHECK-32:       # %bb.0: # %entry
510; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
511; CHECK-32-NEXT:    xxinsertw 34, 0, 12
512; CHECK-32-NEXT:    blr
513entry:
514  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
515  ret <4 x i32> %vecins
516}
517
518define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
519; CHECK-64-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_:
520; CHECK-64:       # %bb.0: # %entry
521; CHECK-64-NEXT:    xxswapd 0, 35
522; CHECK-64-NEXT:    xxinsertw 34, 0, 12
523; CHECK-64-NEXT:    blr
524;
525; CHECK-32-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_:
526; CHECK-32:       # %bb.0: # %entry
527; CHECK-32-NEXT:    xxswapd 0, 35
528; CHECK-32-NEXT:    xxinsertw 34, 0, 12
529; CHECK-32-NEXT:    blr
530entry:
531  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
532  ret <4 x i32> %vecins
533}
534
535define float @_Z13testUiToFpExtILj0EEfDv4_j(<4 x i32> %a) {
536; CHECK-64-LABEL: _Z13testUiToFpExtILj0EEfDv4_j:
537; CHECK-64:       # %bb.0: # %entry
538; CHECK-64-NEXT:    xxextractuw 0, 34, 0
539; CHECK-64-NEXT:    xscvuxdsp 1, 0
540; CHECK-64-NEXT:    blr
541;
542; CHECK-32-LABEL: _Z13testUiToFpExtILj0EEfDv4_j:
543; CHECK-32:       # %bb.0: # %entry
544; CHECK-32-NEXT:    stxv 34, -32(1)
545; CHECK-32-NEXT:    lwz 3, -32(1)
546; CHECK-32-NEXT:    stw 3, -4(1)
547; CHECK-32-NEXT:    addi 3, 1, -4
548; CHECK-32-NEXT:    lfiwzx 0, 0, 3
549; CHECK-32-NEXT:    xscvuxdsp 1, 0
550; CHECK-32-NEXT:    blr
551entry:
552  %vecext = extractelement <4 x i32> %a, i32 0
553  %conv = uitofp i32 %vecext to float
554  ret float %conv
555}
556
557define float @_Z13testUiToFpExtILj1EEfDv4_j(<4 x i32> %a) {
558; CHECK-64-LABEL: _Z13testUiToFpExtILj1EEfDv4_j:
559; CHECK-64:       # %bb.0: # %entry
560; CHECK-64-NEXT:    xxextractuw 0, 34, 4
561; CHECK-64-NEXT:    xscvuxdsp 1, 0
562; CHECK-64-NEXT:    blr
563;
564; CHECK-32-LABEL: _Z13testUiToFpExtILj1EEfDv4_j:
565; CHECK-32:       # %bb.0: # %entry
566; CHECK-32-NEXT:    stxv 34, -32(1)
567; CHECK-32-NEXT:    lwz 3, -28(1)
568; CHECK-32-NEXT:    stw 3, -4(1)
569; CHECK-32-NEXT:    addi 3, 1, -4
570; CHECK-32-NEXT:    lfiwzx 0, 0, 3
571; CHECK-32-NEXT:    xscvuxdsp 1, 0
572; CHECK-32-NEXT:    blr
573entry:
574  %vecext = extractelement <4 x i32> %a, i32 1
575  %conv = uitofp i32 %vecext to float
576  ret float %conv
577}
578
579define float @_Z13testUiToFpExtILj2EEfDv4_j(<4 x i32> %a) {
580; CHECK-64-LABEL: _Z13testUiToFpExtILj2EEfDv4_j:
581; CHECK-64:       # %bb.0: # %entry
582; CHECK-64-NEXT:    xxextractuw 0, 34, 8
583; CHECK-64-NEXT:    xscvuxdsp 1, 0
584; CHECK-64-NEXT:    blr
585;
586; CHECK-32-LABEL: _Z13testUiToFpExtILj2EEfDv4_j:
587; CHECK-32:       # %bb.0: # %entry
588; CHECK-32-NEXT:    stxv 34, -32(1)
589; CHECK-32-NEXT:    lwz 3, -24(1)
590; CHECK-32-NEXT:    stw 3, -4(1)
591; CHECK-32-NEXT:    addi 3, 1, -4
592; CHECK-32-NEXT:    lfiwzx 0, 0, 3
593; CHECK-32-NEXT:    xscvuxdsp 1, 0
594; CHECK-32-NEXT:    blr
595entry:
596  %vecext = extractelement <4 x i32> %a, i32 2
597  %conv = uitofp i32 %vecext to float
598  ret float %conv
599}
600
601define float @_Z13testUiToFpExtILj3EEfDv4_j(<4 x i32> %a) {
602; CHECK-64-LABEL: _Z13testUiToFpExtILj3EEfDv4_j:
603; CHECK-64:       # %bb.0: # %entry
604; CHECK-64-NEXT:    xxextractuw 0, 34, 12
605; CHECK-64-NEXT:    xscvuxdsp 1, 0
606; CHECK-64-NEXT:    blr
607;
608; CHECK-32-LABEL: _Z13testUiToFpExtILj3EEfDv4_j:
609; CHECK-32:       # %bb.0: # %entry
610; CHECK-32-NEXT:    stxv 34, -32(1)
611; CHECK-32-NEXT:    lwz 3, -20(1)
612; CHECK-32-NEXT:    stw 3, -4(1)
613; CHECK-32-NEXT:    addi 3, 1, -4
614; CHECK-32-NEXT:    lfiwzx 0, 0, 3
615; CHECK-32-NEXT:    xscvuxdsp 1, 0
616; CHECK-32-NEXT:    blr
617entry:
618  %vecext = extractelement <4 x i32> %a, i32 3
619  %conv = uitofp i32 %vecext to float
620  ret float %conv
621}
622
623; Verify we generate optimal code for unsigned vector int elem extract followed
624; by conversion to double
625
626define double @conv2dlbTestui0(<4 x i32> %a) {
627; CHECK-64-LABEL: conv2dlbTestui0:
628; CHECK-64:       # %bb.0: # %entry
629; CHECK-64-NEXT:    xxextractuw 0, 34, 0
630; CHECK-64-NEXT:    xscvuxddp 1, 0
631; CHECK-64-NEXT:    blr
632;
633; CHECK-32-LABEL: conv2dlbTestui0:
634; CHECK-32:       # %bb.0: # %entry
635; CHECK-32-NEXT:    stxv 34, -32(1)
636; CHECK-32-NEXT:    lwz 3, -32(1)
637; CHECK-32-NEXT:    stw 3, -4(1)
638; CHECK-32-NEXT:    addi 3, 1, -4
639; CHECK-32-NEXT:    lfiwzx 0, 0, 3
640; CHECK-32-NEXT:    xscvuxddp 1, 0
641; CHECK-32-NEXT:    blr
642entry:
643  %0 = extractelement <4 x i32> %a, i32 0
644  %1 = uitofp i32 %0 to double
645  ret double %1
646}
647
648define double @conv2dlbTestui1(<4 x i32> %a) {
649; CHECK-64-LABEL: conv2dlbTestui1:
650; CHECK-64:       # %bb.0: # %entry
651; CHECK-64-NEXT:    xxextractuw 0, 34, 4
652; CHECK-64-NEXT:    xscvuxddp 1, 0
653; CHECK-64-NEXT:    blr
654;
655; CHECK-32-LABEL: conv2dlbTestui1:
656; CHECK-32:       # %bb.0: # %entry
657; CHECK-32-NEXT:    stxv 34, -32(1)
658; CHECK-32-NEXT:    lwz 3, -28(1)
659; CHECK-32-NEXT:    stw 3, -4(1)
660; CHECK-32-NEXT:    addi 3, 1, -4
661; CHECK-32-NEXT:    lfiwzx 0, 0, 3
662; CHECK-32-NEXT:    xscvuxddp 1, 0
663; CHECK-32-NEXT:    blr
664entry:
665  %0 = extractelement <4 x i32> %a, i32 1
666  %1 = uitofp i32 %0 to double
667  ret double %1
668}
669
670define double @conv2dlbTestui2(<4 x i32> %a) {
671; CHECK-64-LABEL: conv2dlbTestui2:
672; CHECK-64:       # %bb.0: # %entry
673; CHECK-64-NEXT:    xxextractuw 0, 34, 8
674; CHECK-64-NEXT:    xscvuxddp 1, 0
675; CHECK-64-NEXT:    blr
676;
677; CHECK-32-LABEL: conv2dlbTestui2:
678; CHECK-32:       # %bb.0: # %entry
679; CHECK-32-NEXT:    stxv 34, -32(1)
680; CHECK-32-NEXT:    lwz 3, -24(1)
681; CHECK-32-NEXT:    stw 3, -4(1)
682; CHECK-32-NEXT:    addi 3, 1, -4
683; CHECK-32-NEXT:    lfiwzx 0, 0, 3
684; CHECK-32-NEXT:    xscvuxddp 1, 0
685; CHECK-32-NEXT:    blr
686entry:
687  %0 = extractelement <4 x i32> %a, i32 2
688  %1 = uitofp i32 %0 to double
689  ret double %1
690}
691
692define double @conv2dlbTestui3(<4 x i32> %a) {
693; CHECK-64-LABEL: conv2dlbTestui3:
694; CHECK-64:       # %bb.0: # %entry
695; CHECK-64-NEXT:    xxextractuw 0, 34, 12
696; CHECK-64-NEXT:    xscvuxddp 1, 0
697; CHECK-64-NEXT:    blr
698;
699; CHECK-32-LABEL: conv2dlbTestui3:
700; CHECK-32:       # %bb.0: # %entry
701; CHECK-32-NEXT:    stxv 34, -32(1)
702; CHECK-32-NEXT:    lwz 3, -20(1)
703; CHECK-32-NEXT:    stw 3, -4(1)
704; CHECK-32-NEXT:    addi 3, 1, -4
705; CHECK-32-NEXT:    lfiwzx 0, 0, 3
706; CHECK-32-NEXT:    xscvuxddp 1, 0
707; CHECK-32-NEXT:    blr
708entry:
709  %0 = extractelement <4 x i32> %a, i32 3
710  %1 = uitofp i32 %0 to double
711  ret double %1
712}
713
714; verify we don't crash for variable elem extract
715define double @conv2dlbTestuiVar(<4 x i32> %a, i32 zeroext %elem) {
716; CHECK-64-LABEL: conv2dlbTestuiVar:
717; CHECK-64:       # %bb.0: # %entry
718; CHECK-64-NEXT:    rlwinm 3, 3, 2, 28, 29
719; CHECK-64-NEXT:    vextuwlx 3, 3, 2
720; CHECK-64-NEXT:    mtfprwz 0, 3
721; CHECK-64-NEXT:    xscvuxddp 1, 0
722; CHECK-64-NEXT:    blr
723;
724; CHECK-32-LABEL: conv2dlbTestuiVar:
725; CHECK-32:       # %bb.0: # %entry
726; CHECK-32-NEXT:    addi 4, 1, -32
727; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
728; CHECK-32-NEXT:    stxv 34, -32(1)
729; CHECK-32-NEXT:    lwzx 3, 4, 3
730; CHECK-32-NEXT:    stw 3, -4(1)
731; CHECK-32-NEXT:    addi 3, 1, -4
732; CHECK-32-NEXT:    lfiwzx 0, 0, 3
733; CHECK-32-NEXT:    xscvuxddp 1, 0
734; CHECK-32-NEXT:    blr
735entry:
736  %vecext = extractelement <4 x i32> %a, i32 %elem
737  %conv = uitofp i32 %vecext to double
738  ret double %conv
739}
740
741define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
742; CHECK-64-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_:
743; CHECK-64:       # %bb.0: # %entry
744; CHECK-64-NEXT:    xscvdpspn 0, 1
745; CHECK-64-NEXT:    xxinsertw 34, 0, 0
746; CHECK-64-NEXT:    blr
747;
748; CHECK-32-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_:
749; CHECK-32:       # %bb.0: # %entry
750; CHECK-32-NEXT:    xscvdpspn 0, 1
751; CHECK-32-NEXT:    xxinsertw 34, 0, 0
752; CHECK-32-NEXT:    blr
753entry:
754  %vecins = insertelement <4 x float> %a, float %b, i32 0
755  ret <4 x float> %vecins
756}
757
758define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
759; CHECK-64-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_:
760; CHECK-64:       # %bb.0: # %entry
761; CHECK-64-NEXT:    xscvdpspn 0, 1
762; CHECK-64-NEXT:    xxinsertw 34, 0, 4
763; CHECK-64-NEXT:    blr
764;
765; CHECK-32-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_:
766; CHECK-32:       # %bb.0: # %entry
767; CHECK-32-NEXT:    xscvdpspn 0, 1
768; CHECK-32-NEXT:    xxinsertw 34, 0, 4
769; CHECK-32-NEXT:    blr
770entry:
771  %vecins = insertelement <4 x float> %a, float %b, i32 1
772  ret <4 x float> %vecins
773}
774
775define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
776; CHECK-64-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_:
777; CHECK-64:       # %bb.0: # %entry
778; CHECK-64-NEXT:    xscvdpspn 0, 1
779; CHECK-64-NEXT:    xxinsertw 34, 0, 8
780; CHECK-64-NEXT:    blr
781;
782; CHECK-32-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_:
783; CHECK-32:       # %bb.0: # %entry
784; CHECK-32-NEXT:    xscvdpspn 0, 1
785; CHECK-32-NEXT:    xxinsertw 34, 0, 8
786; CHECK-32-NEXT:    blr
787entry:
788  %vecins = insertelement <4 x float> %a, float %b, i32 2
789  ret <4 x float> %vecins
790}
791
792define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
793; CHECK-64-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_:
794; CHECK-64:       # %bb.0: # %entry
795; CHECK-64-NEXT:    xscvdpspn 0, 1
796; CHECK-64-NEXT:    xxinsertw 34, 0, 12
797; CHECK-64-NEXT:    blr
798;
799; CHECK-32-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_:
800; CHECK-32:       # %bb.0: # %entry
801; CHECK-32-NEXT:    xscvdpspn 0, 1
802; CHECK-32-NEXT:    xxinsertw 34, 0, 12
803; CHECK-32-NEXT:    blr
804entry:
805  %vecins = insertelement <4 x float> %a, float %b, i32 3
806  ret <4 x float> %vecins
807}
808
809define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
810; CHECK-64-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_:
811; CHECK-64:       # %bb.0: # %entry
812; CHECK-64-NEXT:    mtfprwz 0, 3
813; CHECK-64-NEXT:    xxinsertw 34, 0, 0
814; CHECK-64-NEXT:    blr
815;
816; CHECK-32-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_:
817; CHECK-32:       # %bb.0: # %entry
818; CHECK-32-NEXT:    mtfprwz 0, 3
819; CHECK-32-NEXT:    xxinsertw 34, 0, 0
820; CHECK-32-NEXT:    blr
821entry:
822  %vecins = insertelement <4 x i32> %a, i32 %b, i32 0
823  ret <4 x i32> %vecins
824}
825
826define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
827; CHECK-64-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_:
828; CHECK-64:       # %bb.0: # %entry
829; CHECK-64-NEXT:    mtfprwz 0, 3
830; CHECK-64-NEXT:    xxinsertw 34, 0, 4
831; CHECK-64-NEXT:    blr
832;
833; CHECK-32-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_:
834; CHECK-32:       # %bb.0: # %entry
835; CHECK-32-NEXT:    mtfprwz 0, 3
836; CHECK-32-NEXT:    xxinsertw 34, 0, 4
837; CHECK-32-NEXT:    blr
838entry:
839  %vecins = insertelement <4 x i32> %a, i32 %b, i32 1
840  ret <4 x i32> %vecins
841}
842
843define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
844; CHECK-64-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_:
845; CHECK-64:       # %bb.0: # %entry
846; CHECK-64-NEXT:    mtfprwz 0, 3
847; CHECK-64-NEXT:    xxinsertw 34, 0, 8
848; CHECK-64-NEXT:    blr
849;
850; CHECK-32-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_:
851; CHECK-32:       # %bb.0: # %entry
852; CHECK-32-NEXT:    mtfprwz 0, 3
853; CHECK-32-NEXT:    xxinsertw 34, 0, 8
854; CHECK-32-NEXT:    blr
855entry:
856  %vecins = insertelement <4 x i32> %a, i32 %b, i32 2
857  ret <4 x i32> %vecins
858}
859
860define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
861; CHECK-64-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_:
862; CHECK-64:       # %bb.0: # %entry
863; CHECK-64-NEXT:    mtfprwz 0, 3
864; CHECK-64-NEXT:    xxinsertw 34, 0, 12
865; CHECK-64-NEXT:    blr
866;
867; CHECK-32-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_:
868; CHECK-32:       # %bb.0: # %entry
869; CHECK-32-NEXT:    mtfprwz 0, 3
870; CHECK-32-NEXT:    xxinsertw 34, 0, 12
871; CHECK-32-NEXT:    blr
872entry:
873  %vecins = insertelement <4 x i32> %a, i32 %b, i32 3
874  ret <4 x i32> %vecins
875}
876
877define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
878; CHECK-64-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_r:
879; CHECK-64:       # %bb.0: # %entry
880; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
881; CHECK-64-NEXT:    xxinsertw 34, 0, 0
882; CHECK-64-NEXT:    blr
883;
884; CHECK-32-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_r:
885; CHECK-32:       # %bb.0: # %entry
886; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
887; CHECK-32-NEXT:    xxinsertw 34, 0, 0
888; CHECK-32-NEXT:    blr
889entry:
890  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
891  ret <4 x float> %vecins
892}
893
894define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
895; CHECK-64-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_r:
896; CHECK-64:       # %bb.0: # %entry
897; CHECK-64-NEXT:    xxinsertw 34, 35, 0
898; CHECK-64-NEXT:    blr
899;
900; CHECK-32-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_r:
901; CHECK-32:       # %bb.0: # %entry
902; CHECK-32-NEXT:    xxinsertw 34, 35, 0
903; CHECK-32-NEXT:    blr
904entry:
905  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>
906  ret <4 x float> %vecins
907}
908
909define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
910; CHECK-64-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_r:
911; CHECK-64:       # %bb.0: # %entry
912; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
913; CHECK-64-NEXT:    xxinsertw 34, 0, 0
914; CHECK-64-NEXT:    blr
915;
916; CHECK-32-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_r:
917; CHECK-32:       # %bb.0: # %entry
918; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
919; CHECK-32-NEXT:    xxinsertw 34, 0, 0
920; CHECK-32-NEXT:    blr
921entry:
922  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>
923  ret <4 x float> %vecins
924}
925
926define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
927; CHECK-64-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_r:
928; CHECK-64:       # %bb.0: # %entry
929; CHECK-64-NEXT:    xxswapd 0, 35
930; CHECK-64-NEXT:    xxinsertw 34, 0, 0
931; CHECK-64-NEXT:    blr
932;
933; CHECK-32-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_r:
934; CHECK-32:       # %bb.0: # %entry
935; CHECK-32-NEXT:    xxswapd 0, 35
936; CHECK-32-NEXT:    xxinsertw 34, 0, 0
937; CHECK-32-NEXT:    blr
938entry:
939  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>
940  ret <4 x float> %vecins
941}
942
943define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
944; CHECK-64-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_r:
945; CHECK-64:       # %bb.0: # %entry
946; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
947; CHECK-64-NEXT:    xxinsertw 34, 0, 4
948; CHECK-64-NEXT:    blr
949;
950; CHECK-32-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_r:
951; CHECK-32:       # %bb.0: # %entry
952; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
953; CHECK-32-NEXT:    xxinsertw 34, 0, 4
954; CHECK-32-NEXT:    blr
955entry:
956  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
957  ret <4 x float> %vecins
958}
959
960define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
961; CHECK-64-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_r:
962; CHECK-64:       # %bb.0: # %entry
963; CHECK-64-NEXT:    xxinsertw 34, 35, 4
964; CHECK-64-NEXT:    blr
965;
966; CHECK-32-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_r:
967; CHECK-32:       # %bb.0: # %entry
968; CHECK-32-NEXT:    xxinsertw 34, 35, 4
969; CHECK-32-NEXT:    blr
970entry:
971  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
972  ret <4 x float> %vecins
973}
974
975define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
976; CHECK-64-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_r:
977; CHECK-64:       # %bb.0: # %entry
978; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
979; CHECK-64-NEXT:    xxinsertw 34, 0, 4
980; CHECK-64-NEXT:    blr
981;
982; CHECK-32-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_r:
983; CHECK-32:       # %bb.0: # %entry
984; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
985; CHECK-32-NEXT:    xxinsertw 34, 0, 4
986; CHECK-32-NEXT:    blr
987entry:
988  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>
989  ret <4 x float> %vecins
990}
991
992define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
993; CHECK-64-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_r:
994; CHECK-64:       # %bb.0: # %entry
995; CHECK-64-NEXT:    xxswapd 0, 35
996; CHECK-64-NEXT:    xxinsertw 34, 0, 4
997; CHECK-64-NEXT:    blr
998;
999; CHECK-32-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_r:
1000; CHECK-32:       # %bb.0: # %entry
1001; CHECK-32-NEXT:    xxswapd 0, 35
1002; CHECK-32-NEXT:    xxinsertw 34, 0, 4
1003; CHECK-32-NEXT:    blr
1004entry:
1005  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>
1006  ret <4 x float> %vecins
1007}
1008
1009define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
1010; CHECK-64-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_r:
1011; CHECK-64:       # %bb.0: # %entry
1012; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
1013; CHECK-64-NEXT:    xxinsertw 34, 0, 8
1014; CHECK-64-NEXT:    blr
1015;
1016; CHECK-32-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_r:
1017; CHECK-32:       # %bb.0: # %entry
1018; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
1019; CHECK-32-NEXT:    xxinsertw 34, 0, 8
1020; CHECK-32-NEXT:    blr
1021entry:
1022  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
1023  ret <4 x float> %vecins
1024}
1025
1026define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
1027; CHECK-64-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_r:
1028; CHECK-64:       # %bb.0: # %entry
1029; CHECK-64-NEXT:    xxinsertw 34, 35, 8
1030; CHECK-64-NEXT:    blr
1031;
1032; CHECK-32-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_r:
1033; CHECK-32:       # %bb.0: # %entry
1034; CHECK-32-NEXT:    xxinsertw 34, 35, 8
1035; CHECK-32-NEXT:    blr
1036entry:
1037  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>
1038  ret <4 x float> %vecins
1039}
1040
1041define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
1042; CHECK-64-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_r:
1043; CHECK-64:       # %bb.0: # %entry
1044; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
1045; CHECK-64-NEXT:    xxinsertw 34, 0, 8
1046; CHECK-64-NEXT:    blr
1047;
1048; CHECK-32-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_r:
1049; CHECK-32:       # %bb.0: # %entry
1050; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
1051; CHECK-32-NEXT:    xxinsertw 34, 0, 8
1052; CHECK-32-NEXT:    blr
1053entry:
1054  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1055  ret <4 x float> %vecins
1056}
1057
1058define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
1059; CHECK-64-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_r:
1060; CHECK-64:       # %bb.0: # %entry
1061; CHECK-64-NEXT:    xxswapd 0, 35
1062; CHECK-64-NEXT:    xxinsertw 34, 0, 8
1063; CHECK-64-NEXT:    blr
1064;
1065; CHECK-32-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_r:
1066; CHECK-32:       # %bb.0: # %entry
1067; CHECK-32-NEXT:    xxswapd 0, 35
1068; CHECK-32-NEXT:    xxinsertw 34, 0, 8
1069; CHECK-32-NEXT:    blr
1070entry:
1071  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>
1072  ret <4 x float> %vecins
1073}
1074
1075define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
1076; CHECK-64-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_r:
1077; CHECK-64:       # %bb.0: # %entry
1078; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
1079; CHECK-64-NEXT:    xxinsertw 34, 0, 12
1080; CHECK-64-NEXT:    blr
1081;
1082; CHECK-32-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_r:
1083; CHECK-32:       # %bb.0: # %entry
1084; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
1085; CHECK-32-NEXT:    xxinsertw 34, 0, 12
1086; CHECK-32-NEXT:    blr
1087entry:
1088  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>
1089  ret <4 x float> %vecins
1090}
1091
1092define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
1093; CHECK-64-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_r:
1094; CHECK-64:       # %bb.0: # %entry
1095; CHECK-64-NEXT:    xxinsertw 34, 35, 12
1096; CHECK-64-NEXT:    blr
1097;
1098; CHECK-32-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_r:
1099; CHECK-32:       # %bb.0: # %entry
1100; CHECK-32-NEXT:    xxinsertw 34, 35, 12
1101; CHECK-32-NEXT:    blr
1102entry:
1103  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>
1104  ret <4 x float> %vecins
1105}
1106
1107define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
1108; CHECK-64-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_r:
1109; CHECK-64:       # %bb.0: # %entry
1110; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
1111; CHECK-64-NEXT:    xxinsertw 34, 0, 12
1112; CHECK-64-NEXT:    blr
1113;
1114; CHECK-32-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_r:
1115; CHECK-32:       # %bb.0: # %entry
1116; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
1117; CHECK-32-NEXT:    xxinsertw 34, 0, 12
1118; CHECK-32-NEXT:    blr
1119entry:
1120  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>
1121  ret <4 x float> %vecins
1122}
1123
1124define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
1125; CHECK-64-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_r:
1126; CHECK-64:       # %bb.0: # %entry
1127; CHECK-64-NEXT:    xxswapd 0, 35
1128; CHECK-64-NEXT:    xxinsertw 34, 0, 12
1129; CHECK-64-NEXT:    blr
1130;
1131; CHECK-32-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_r:
1132; CHECK-32:       # %bb.0: # %entry
1133; CHECK-32-NEXT:    xxswapd 0, 35
1134; CHECK-32-NEXT:    xxinsertw 34, 0, 12
1135; CHECK-32-NEXT:    blr
1136entry:
1137  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>
1138  ret <4 x float> %vecins
1139}
1140
1141define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1142; CHECK-64-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_r:
1143; CHECK-64:       # %bb.0: # %entry
1144; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
1145; CHECK-64-NEXT:    xxinsertw 34, 0, 0
1146; CHECK-64-NEXT:    blr
1147;
1148; CHECK-32-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_r:
1149; CHECK-32:       # %bb.0: # %entry
1150; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
1151; CHECK-32-NEXT:    xxinsertw 34, 0, 0
1152; CHECK-32-NEXT:    blr
1153entry:
1154  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1155  ret <4 x i32> %vecins
1156}
1157
1158define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1159; CHECK-64-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_r:
1160; CHECK-64:       # %bb.0: # %entry
1161; CHECK-64-NEXT:    xxinsertw 34, 35, 0
1162; CHECK-64-NEXT:    blr
1163;
1164; CHECK-32-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_r:
1165; CHECK-32:       # %bb.0: # %entry
1166; CHECK-32-NEXT:    xxinsertw 34, 35, 0
1167; CHECK-32-NEXT:    blr
1168entry:
1169  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>
1170  ret <4 x i32> %vecins
1171}
1172
1173define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1174; CHECK-64-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_r:
1175; CHECK-64:       # %bb.0: # %entry
1176; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
1177; CHECK-64-NEXT:    xxinsertw 34, 0, 0
1178; CHECK-64-NEXT:    blr
1179;
1180; CHECK-32-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_r:
1181; CHECK-32:       # %bb.0: # %entry
1182; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
1183; CHECK-32-NEXT:    xxinsertw 34, 0, 0
1184; CHECK-32-NEXT:    blr
1185entry:
1186  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>
1187  ret <4 x i32> %vecins
1188}
1189
1190define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1191; CHECK-64-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_r:
1192; CHECK-64:       # %bb.0: # %entry
1193; CHECK-64-NEXT:    xxswapd 0, 35
1194; CHECK-64-NEXT:    xxinsertw 34, 0, 0
1195; CHECK-64-NEXT:    blr
1196;
1197; CHECK-32-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_r:
1198; CHECK-32:       # %bb.0: # %entry
1199; CHECK-32-NEXT:    xxswapd 0, 35
1200; CHECK-32-NEXT:    xxinsertw 34, 0, 0
1201; CHECK-32-NEXT:    blr
1202entry:
1203  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>
1204  ret <4 x i32> %vecins
1205}
1206
1207define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1208; CHECK-64-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_r:
1209; CHECK-64:       # %bb.0: # %entry
1210; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
1211; CHECK-64-NEXT:    xxinsertw 34, 0, 4
1212; CHECK-64-NEXT:    blr
1213;
1214; CHECK-32-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_r:
1215; CHECK-32:       # %bb.0: # %entry
1216; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
1217; CHECK-32-NEXT:    xxinsertw 34, 0, 4
1218; CHECK-32-NEXT:    blr
1219entry:
1220  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
1221  ret <4 x i32> %vecins
1222}
1223
1224define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1225; CHECK-64-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_r:
1226; CHECK-64:       # %bb.0: # %entry
1227; CHECK-64-NEXT:    xxinsertw 34, 35, 4
1228; CHECK-64-NEXT:    blr
1229;
1230; CHECK-32-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_r:
1231; CHECK-32:       # %bb.0: # %entry
1232; CHECK-32-NEXT:    xxinsertw 34, 35, 4
1233; CHECK-32-NEXT:    blr
1234entry:
1235  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1236  ret <4 x i32> %vecins
1237}
1238
1239define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1240; CHECK-64-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_r:
1241; CHECK-64:       # %bb.0: # %entry
1242; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
1243; CHECK-64-NEXT:    xxinsertw 34, 0, 4
1244; CHECK-64-NEXT:    blr
1245;
1246; CHECK-32-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_r:
1247; CHECK-32:       # %bb.0: # %entry
1248; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
1249; CHECK-32-NEXT:    xxinsertw 34, 0, 4
1250; CHECK-32-NEXT:    blr
1251entry:
1252  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>
1253  ret <4 x i32> %vecins
1254}
1255
1256define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1257; CHECK-64-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_r:
1258; CHECK-64:       # %bb.0: # %entry
1259; CHECK-64-NEXT:    xxswapd 0, 35
1260; CHECK-64-NEXT:    xxinsertw 34, 0, 4
1261; CHECK-64-NEXT:    blr
1262;
1263; CHECK-32-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_r:
1264; CHECK-32:       # %bb.0: # %entry
1265; CHECK-32-NEXT:    xxswapd 0, 35
1266; CHECK-32-NEXT:    xxinsertw 34, 0, 4
1267; CHECK-32-NEXT:    blr
1268entry:
1269  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>
1270  ret <4 x i32> %vecins
1271}
1272
1273define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1274; CHECK-64-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_r:
1275; CHECK-64:       # %bb.0: # %entry
1276; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
1277; CHECK-64-NEXT:    xxinsertw 34, 0, 8
1278; CHECK-64-NEXT:    blr
1279;
1280; CHECK-32-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_r:
1281; CHECK-32:       # %bb.0: # %entry
1282; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
1283; CHECK-32-NEXT:    xxinsertw 34, 0, 8
1284; CHECK-32-NEXT:    blr
1285entry:
1286  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
1287  ret <4 x i32> %vecins
1288}
1289
1290define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1291; CHECK-64-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_r:
1292; CHECK-64:       # %bb.0: # %entry
1293; CHECK-64-NEXT:    xxinsertw 34, 35, 8
1294; CHECK-64-NEXT:    blr
1295;
1296; CHECK-32-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_r:
1297; CHECK-32:       # %bb.0: # %entry
1298; CHECK-32-NEXT:    xxinsertw 34, 35, 8
1299; CHECK-32-NEXT:    blr
1300entry:
1301  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>
1302  ret <4 x i32> %vecins
1303}
1304
1305define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1306; CHECK-64-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_r:
1307; CHECK-64:       # %bb.0: # %entry
1308; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
1309; CHECK-64-NEXT:    xxinsertw 34, 0, 8
1310; CHECK-64-NEXT:    blr
1311;
1312; CHECK-32-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_r:
1313; CHECK-32:       # %bb.0: # %entry
1314; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
1315; CHECK-32-NEXT:    xxinsertw 34, 0, 8
1316; CHECK-32-NEXT:    blr
1317entry:
1318  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1319  ret <4 x i32> %vecins
1320}
1321
1322define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1323; CHECK-64-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_r:
1324; CHECK-64:       # %bb.0: # %entry
1325; CHECK-64-NEXT:    xxswapd 0, 35
1326; CHECK-64-NEXT:    xxinsertw 34, 0, 8
1327; CHECK-64-NEXT:    blr
1328;
1329; CHECK-32-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_r:
1330; CHECK-32:       # %bb.0: # %entry
1331; CHECK-32-NEXT:    xxswapd 0, 35
1332; CHECK-32-NEXT:    xxinsertw 34, 0, 8
1333; CHECK-32-NEXT:    blr
1334entry:
1335  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>
1336  ret <4 x i32> %vecins
1337}
1338
1339define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1340; CHECK-64-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_r:
1341; CHECK-64:       # %bb.0: # %entry
1342; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 3
1343; CHECK-64-NEXT:    xxinsertw 34, 0, 12
1344; CHECK-64-NEXT:    blr
1345;
1346; CHECK-32-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_r:
1347; CHECK-32:       # %bb.0: # %entry
1348; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 3
1349; CHECK-32-NEXT:    xxinsertw 34, 0, 12
1350; CHECK-32-NEXT:    blr
1351entry:
1352  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>
1353  ret <4 x i32> %vecins
1354}
1355
1356define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1357; CHECK-64-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_r:
1358; CHECK-64:       # %bb.0: # %entry
1359; CHECK-64-NEXT:    xxinsertw 34, 35, 12
1360; CHECK-64-NEXT:    blr
1361;
1362; CHECK-32-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_r:
1363; CHECK-32:       # %bb.0: # %entry
1364; CHECK-32-NEXT:    xxinsertw 34, 35, 12
1365; CHECK-32-NEXT:    blr
1366entry:
1367  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>
1368  ret <4 x i32> %vecins
1369}
1370
1371define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1372; CHECK-64-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_r:
1373; CHECK-64:       # %bb.0: # %entry
1374; CHECK-64-NEXT:    xxsldwi 0, 35, 35, 1
1375; CHECK-64-NEXT:    xxinsertw 34, 0, 12
1376; CHECK-64-NEXT:    blr
1377;
1378; CHECK-32-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_r:
1379; CHECK-32:       # %bb.0: # %entry
1380; CHECK-32-NEXT:    xxsldwi 0, 35, 35, 1
1381; CHECK-32-NEXT:    xxinsertw 34, 0, 12
1382; CHECK-32-NEXT:    blr
1383entry:
1384  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>
1385  ret <4 x i32> %vecins
1386}
1387
1388define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
1389; CHECK-64-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_r:
1390; CHECK-64:       # %bb.0: # %entry
1391; CHECK-64-NEXT:    xxswapd 0, 35
1392; CHECK-64-NEXT:    xxinsertw 34, 0, 12
1393; CHECK-64-NEXT:    blr
1394;
1395; CHECK-32-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_r:
1396; CHECK-32:       # %bb.0: # %entry
1397; CHECK-32-NEXT:    xxswapd 0, 35
1398; CHECK-32-NEXT:    xxinsertw 34, 0, 12
1399; CHECK-32-NEXT:    blr
1400entry:
1401  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>
1402  ret <4 x i32> %vecins
1403}
1404define <4 x float> @testSameVecEl0BE(<4 x float> %a) {
1405; CHECK-64-LABEL: testSameVecEl0BE:
1406; CHECK-64:       # %bb.0: # %entry
1407; CHECK-64-NEXT:    xxinsertw 34, 34, 0
1408; CHECK-64-NEXT:    blr
1409;
1410; CHECK-32-LABEL: testSameVecEl0BE:
1411; CHECK-32:       # %bb.0: # %entry
1412; CHECK-32-NEXT:    xxinsertw 34, 34, 0
1413; CHECK-32-NEXT:    blr
1414entry:
1415  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
1416  ret <4 x float> %vecins
1417}
1418define <4 x float> @testSameVecEl2BE(<4 x float> %a) {
1419; CHECK-64-LABEL: testSameVecEl2BE:
1420; CHECK-64:       # %bb.0: # %entry
1421; CHECK-64-NEXT:    xxinsertw 34, 34, 8
1422; CHECK-64-NEXT:    blr
1423;
1424; CHECK-32-LABEL: testSameVecEl2BE:
1425; CHECK-32:       # %bb.0: # %entry
1426; CHECK-32-NEXT:    xxinsertw 34, 34, 8
1427; CHECK-32-NEXT:    blr
1428entry:
1429  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
1430  ret <4 x float> %vecins
1431}
1432define <4 x float> @testSameVecEl3BE(<4 x float> %a) {
1433; CHECK-64-LABEL: testSameVecEl3BE:
1434; CHECK-64:       # %bb.0: # %entry
1435; CHECK-64-NEXT:    xxinsertw 34, 34, 12
1436; CHECK-64-NEXT:    blr
1437;
1438; CHECK-32-LABEL: testSameVecEl3BE:
1439; CHECK-32:       # %bb.0: # %entry
1440; CHECK-32-NEXT:    xxinsertw 34, 34, 12
1441; CHECK-32-NEXT:    blr
1442entry:
1443  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
1444  ret <4 x float> %vecins
1445}
1446define <4 x float> @testSameVecEl0LE(<4 x float> %a) {
1447; CHECK-64-LABEL: testSameVecEl0LE:
1448; CHECK-64:       # %bb.0: # %entry
1449; CHECK-64-NEXT:    ld 3, L..C0(2) # %const.0
1450; CHECK-64-NEXT:    lxv 0, 0(3)
1451; CHECK-64-NEXT:    xxperm 34, 34, 0
1452; CHECK-64-NEXT:    blr
1453;
1454; CHECK-32-LABEL: testSameVecEl0LE:
1455; CHECK-32:       # %bb.0: # %entry
1456; CHECK-32-NEXT:    lwz 3, L..C0(2) # %const.0
1457; CHECK-32-NEXT:    lxv 0, 0(3)
1458; CHECK-32-NEXT:    xxperm 34, 34, 0
1459; CHECK-32-NEXT:    blr
1460entry:
1461  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
1462  ret <4 x float> %vecins
1463}
1464define <4 x float> @testSameVecEl1LE(<4 x float> %a) {
1465; CHECK-64-LABEL: testSameVecEl1LE:
1466; CHECK-64:       # %bb.0: # %entry
1467; CHECK-64-NEXT:    ld 3, L..C1(2) # %const.0
1468; CHECK-64-NEXT:    lxv 0, 0(3)
1469; CHECK-64-NEXT:    xxperm 34, 34, 0
1470; CHECK-64-NEXT:    blr
1471;
1472; CHECK-32-LABEL: testSameVecEl1LE:
1473; CHECK-32:       # %bb.0: # %entry
1474; CHECK-32-NEXT:    lwz 3, L..C1(2) # %const.0
1475; CHECK-32-NEXT:    lxv 0, 0(3)
1476; CHECK-32-NEXT:    xxperm 34, 34, 0
1477; CHECK-32-NEXT:    blr
1478entry:
1479  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
1480  ret <4 x float> %vecins
1481}
1482define <4 x float> @testSameVecEl3LE(<4 x float> %a) {
1483; CHECK-64-LABEL: testSameVecEl3LE:
1484; CHECK-64:       # %bb.0: # %entry
1485; CHECK-64-NEXT:    ld 3, L..C2(2) # %const.0
1486; CHECK-64-NEXT:    lxv 0, 0(3)
1487; CHECK-64-NEXT:    xxperm 34, 34, 0
1488; CHECK-64-NEXT:    blr
1489;
1490; CHECK-32-LABEL: testSameVecEl3LE:
1491; CHECK-32:       # %bb.0: # %entry
1492; CHECK-32-NEXT:    lwz 3, L..C2(2) # %const.0
1493; CHECK-32-NEXT:    lxv 0, 0(3)
1494; CHECK-32-NEXT:    xxperm 34, 34, 0
1495; CHECK-32-NEXT:    blr
1496entry:
1497  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
1498  ret <4 x float> %vecins
1499}
1500define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) {
1501; CHECK-64-LABEL: insertVarF:
1502; CHECK-64:       # %bb.0: # %entry
1503; CHECK-64-NEXT:    rlwinm 3, 4, 2, 28, 29
1504; CHECK-64-NEXT:    addi 4, 1, -16
1505; CHECK-64-NEXT:    stxv 34, -16(1)
1506; CHECK-64-NEXT:    stfsx 1, 4, 3
1507; CHECK-64-NEXT:    lxv 34, -16(1)
1508; CHECK-64-NEXT:    blr
1509;
1510; CHECK-32-LABEL: insertVarF:
1511; CHECK-32:       # %bb.0: # %entry
1512; CHECK-32-NEXT:    rlwinm 3, 4, 2, 28, 29
1513; CHECK-32-NEXT:    addi 4, 1, -16
1514; CHECK-32-NEXT:    stxv 34, -16(1)
1515; CHECK-32-NEXT:    stfsx 1, 4, 3
1516; CHECK-32-NEXT:    lxv 34, -16(1)
1517; CHECK-32-NEXT:    blr
1518entry:
1519  %vecins = insertelement <4 x float> %a, float %f, i32 %el
1520  ret <4 x float> %vecins
1521}
1522define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) {
1523; CHECK-64-LABEL: insertVarI:
1524; CHECK-64:       # %bb.0: # %entry
1525; CHECK-64-NEXT:    addi 5, 1, -16
1526; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
1527; CHECK-64-NEXT:    stxv 34, -16(1)
1528; CHECK-64-NEXT:    stwx 3, 5, 4
1529; CHECK-64-NEXT:    lxv 34, -16(1)
1530; CHECK-64-NEXT:    blr
1531;
1532; CHECK-32-LABEL: insertVarI:
1533; CHECK-32:       # %bb.0: # %entry
1534; CHECK-32-NEXT:    addi 5, 1, -16
1535; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
1536; CHECK-32-NEXT:    stxv 34, -16(1)
1537; CHECK-32-NEXT:    stwx 3, 5, 4
1538; CHECK-32-NEXT:    lxv 34, -16(1)
1539; CHECK-32-NEXT:    blr
1540entry:
1541  %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el
1542  ret <4 x i32> %vecins
1543}
1544define <4 x i32> @intrinsicInsertTest(<4 x i32> %a, <2 x i64> %b) {
1545; CHECK-64-LABEL: intrinsicInsertTest:
1546; CHECK-64:       # %bb.0: # %entry
1547; CHECK-64-NEXT:    xxinsertw 34, 35, 3
1548; CHECK-64-NEXT:    blr
1549;
1550; CHECK-32-LABEL: intrinsicInsertTest:
1551; CHECK-32:       # %bb.0: # %entry
1552; CHECK-32-NEXT:    xxinsertw 34, 35, 3
1553; CHECK-32-NEXT:    blr
1554entry:
1555  %ans = tail call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> %a, <2 x i64> %b, i32 3)
1556  ret <4 x i32> %ans
1557}
1558declare <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>, <2 x i64>, i32)
1559define <2 x i64> @intrinsicExtractTest(<2 x i64> %a) {
1560; CHECK-64-LABEL: intrinsicExtractTest:
1561; CHECK-64:       # %bb.0: # %entry
1562; CHECK-64-NEXT:    xxextractuw 34, 34, 5
1563; CHECK-64-NEXT:    blr
1564;
1565; CHECK-32-LABEL: intrinsicExtractTest:
1566; CHECK-32:       # %bb.0: # %entry
1567; CHECK-32-NEXT:    xxextractuw 34, 34, 5
1568; CHECK-32-NEXT:    blr
1569entry:
1570  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> %a, i32 5)
1571  ret <2 x i64> %ans
1572}
1573declare <2 x i64>  @llvm.ppc.vsx.xxextractuw(<2 x i64>, i32)
1574