xref: /llvm-project/llvm/test/CodeGen/PowerPC/aix-fptoint.ll (revision bf4596bf5862c0a7092507463f6df9e80566a93d)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -O3 -mtriple powerpc-ibm-aix -verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
3; RUN: llc -O3 -mtriple powerpc64-ibm-aix -verify-machineinstrs < %s | FileCheck --check-prefix=64BIT %s
4
5; Function Attrs: nounwind strictfp
6define i64 @tester_s(double %d) local_unnamed_addr #0 {
7; 32BIT-LABEL: tester_s:
8; 32BIT:       # %bb.0: # %entry
9; 32BIT-NEXT:    xscvdpsxds 0, 1
10; 32BIT-NEXT:    stfd 0, -8(1)
11; 32BIT-NEXT:    lwz 3, -8(1)
12; 32BIT-NEXT:    lwz 4, -4(1)
13; 32BIT-NEXT:    blr
14;
15; 64BIT-LABEL: tester_s:
16; 64BIT:       # %bb.0: # %entry
17; 64BIT-NEXT:    xscvdpsxds 0, 1
18; 64BIT-NEXT:    stfd 0, -8(1)
19; 64BIT-NEXT:    ld 3, -8(1)
20; 64BIT-NEXT:    blr
21entry:
22  %conv = tail call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %d, metadata !"fpexcept.ignore") #2
23  ret i64 %conv
24}
25
26; Function Attrs: nounwind strictfp
27define i64 @tester_u(double %d) local_unnamed_addr #0 {
28; 32BIT-LABEL: tester_u:
29; 32BIT:       # %bb.0: # %entry
30; 32BIT-NEXT:    xscvdpuxds 0, 1
31; 32BIT-NEXT:    stfd 0, -8(1)
32; 32BIT-NEXT:    lwz 3, -8(1)
33; 32BIT-NEXT:    lwz 4, -4(1)
34; 32BIT-NEXT:    blr
35;
36; 64BIT-LABEL: tester_u:
37; 64BIT:       # %bb.0: # %entry
38; 64BIT-NEXT:    xscvdpuxds 0, 1
39; 64BIT-NEXT:    stfd 0, -8(1)
40; 64BIT-NEXT:    ld 3, -8(1)
41; 64BIT-NEXT:    blr
42entry:
43  %conv = tail call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %d, metadata !"fpexcept.ignore") #2
44  ret i64 %conv
45}
46
47; Function Attrs: nounwind
48declare i64 @llvm.experimental.constrained.fptosi.i64.f64(double, metadata) #1
49declare i64 @llvm.experimental.constrained.fptoui.i64.f64(double, metadata) #1
50
51attributes #0 = { nounwind strictfp "target-cpu"="pwr7" }
52attributes #1 = { nounwind }
53
54
55