xref: /llvm-project/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir (revision 60442f0d442723a487528bdd8b48b24657a025e8)
1# RUN: llc -o - %s -start-after=if-converter | FileCheck %s
2
3--- |
4  target datalayout = "E-m:e-i64:64-n32:64"
5  target triple = "powerpc64-unknown-linux-gnu"
6
7  %struct.rwlock_t.0.22.58.68.242.244 = type {}
8
9  @tasklist_lock = external global %struct.rwlock_t.0.22.58.68.242.244, align 1
10
11  ; Function Attrs: nounwind
12  define void @mm_update_next_owner(ptr %p1, ptr %p2) #0 {
13  entry:
14    %0 = load ptr, ptr %p1, align 8
15    br i1 undef, label %do.body.92, label %for.body.21
16
17  for.body.21:                                      ; preds = %entry
18    unreachable
19
20  do.body.92:                                       ; preds = %entry
21    %usage = getelementptr inbounds i8, ptr %0, i64 -48
22    %call95 = tail call signext i32 @__raw_read_unlock(ptr nonnull @tasklist_lock) #1
23    store volatile i32 0, ptr %p2, align 4
24    tail call void asm sideeffect "#compiler barrier", "~{memory}"() #1
25    %1 = tail call i32 asm sideeffect "\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", "=&r,r,~{cc},~{xer},~{memory}"(ptr %usage) #1
26    %cmp.i = icmp eq i32 %1, 0
27    br i1 %cmp.i, label %if.then.i, label %put_task_struct.exit
28
29  if.then.i:                                        ; preds = %do.body.92
30    unreachable
31
32  put_task_struct.exit:                             ; preds = %do.body.92
33    ret void
34  }
35
36  declare signext i32 @__raw_read_unlock(...)
37
38  attributes #0 = { nounwind "target-cpu"="pwr7" }
39  attributes #1 = { nounwind }
40
41...
42---
43name:            mm_update_next_owner
44alignment:       16
45exposesReturnsTwice: false
46tracksRegLiveness: true
47liveins:
48  - { reg: '$x3' }
49  - { reg: '$x4' }
50frameInfo:
51  isFrameAddressTaken: false
52  isReturnAddressTaken: false
53  hasStackMap:     false
54  hasPatchPoint:   false
55  stackSize:       144
56  offsetAdjustment: 0
57  maxAlignment:    0
58  adjustsStack:    true
59  hasCalls:        true
60  maxCallFrameSize: 112
61  hasOpaqueSPAdjustment: false
62  hasVAStart:      false
63  hasMustTailInVarArgFunc: false
64fixedStack:
65  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$x30' }
66  - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$x29' }
67body:             |
68  bb.0.entry:
69    liveins: $x3, $x4, $x29, $x30, $x29, $x30
70
71    $x0 = MFLR8 implicit $lr8
72    STD $x0, 16, $x1
73    $x1 = STDU $x1, -144, $x1
74    STD killed $x29, 120, $x1 :: (store (s64) into %fixed-stack.1)
75    STD killed $x30, 128, $x1 :: (store (s64) into %fixed-stack.0, align 16)
76    $x30 = OR8 $x4, $x4
77    $x3 = LD 0, killed $x3 :: (load (s64) from %ir.p1)
78    $x29 = ADDI8 killed $x3, -48
79    $x3 = ADDIStocHA8 $x2, @tasklist_lock
80    $x3 = LDtocL @tasklist_lock, killed $x3, implicit $x2 :: (load (s64) from got)
81    BL8_NOP @__raw_read_unlock, csr_ppc64_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
82    $r3 = LI 0
83    STW killed $r3, 0, killed $x30 :: (volatile store (s32) into %ir.p2)
84    INLINEASM &"#compiler barrier", 25
85    INLINEASM &"\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", 25, 131083, def early-clobber $r3, 851977, killed $x29, 12, implicit-def dead early-clobber $cr0
86    ; CHECK-LABEL: @mm_update_next_owner
87    ; CHECK-NOT: lwarx 29, 0, 29
88    ; CHECK-NOT: stwcx. 29, 0, 29
89    $cr0 = CMPLWI killed $r3, 0
90    $x30 = LD 128, $x1 :: (load (s64) from %fixed-stack.0, align 16)
91    $x29 = LD 120, $x1 :: (load (s64) from %fixed-stack.1)
92    $x1 = ADDI8 $x1, 144
93    $x0 = LD 16, $x1
94    MTLR8 $x0, implicit-def $lr8
95    BLR8 implicit $lr8, implicit $rm
96
97...
98