1; RUN: llc --debugify-and-strip-all-safe=0 -mtriple=powerpc64-- -O3 \ 2; RUN: -debug-pass=Structure < %s -o /dev/null 2>&1 | \ 3; RUN: grep -v "Verify generated machine code" | FileCheck %s 4 5; REQUIRES: asserts 6; CHECK-LABEL: Pass Arguments: 7; CHECK-NEXT: Target Library Information 8; CHECK-NEXT: Target Pass Configuration 9; CHECK-NEXT: Machine Module Information 10; CHECK-NEXT: Target Transform Information 11; CHECK-NEXT: Assumption Cache Tracker 12; CHECK-NEXT: Type-Based Alias Analysis 13; CHECK-NEXT: Scoped NoAlias Alias Analysis 14; CHECK-NEXT: Profile summary info 15; CHECK-NEXT: Create Garbage Collector Module Metadata 16; CHECK-NEXT: Machine Branch Probability Analysis 17; CHECK-NEXT: Default Regalloc Eviction Advisor 18; CHECK-NEXT: Default Regalloc Priority Advisor 19; CHECK-NEXT: ModulePass Manager 20; CHECK-NEXT: Pre-ISel Intrinsic Lowering 21; CHECK-NEXT: FunctionPass Manager 22; CHECK-NEXT: Expand large div/rem 23; CHECK-NEXT: Expand large fp convert 24; CHECK-NEXT: Convert i1 constants to i32/i64 if they are returned 25; CHECK-NEXT: Expand Atomic instructions 26; CHECK-NEXT: PPC Lower MASS Entries 27; CHECK-NEXT: FunctionPass Manager 28; CHECK-NEXT: Dominator Tree Construction 29; CHECK-NEXT: Natural Loop Information 30; CHECK-NEXT: Split GEPs to a variadic base and a constant offset for better CSE 31; CHECK-NEXT: Early CSE 32; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 33; CHECK-NEXT: Function Alias Analysis Results 34; CHECK-NEXT: Memory SSA 35; CHECK-NEXT: Canonicalize natural loops 36; CHECK-NEXT: LCSSA Verifier 37; CHECK-NEXT: Loop-Closed SSA Form Pass 38; CHECK-NEXT: Scalar Evolution Analysis 39; CHECK-NEXT: Lazy Branch Probability Analysis 40; CHECK-NEXT: Lazy Block Frequency Analysis 41; CHECK-NEXT: Loop Pass Manager 42; CHECK-NEXT: Loop Invariant Code Motion 43; CHECK-NEXT: Module Verifier 44; CHECK-NEXT: Loop Pass Manager 45; CHECK-NEXT: Canonicalize Freeze Instructions in Loops 46; CHECK-NEXT: Induction Variable Users 47; CHECK-NEXT: Loop Strength Reduction 48; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 49; CHECK-NEXT: Function Alias Analysis Results 50; CHECK-NEXT: Merge contiguous icmps into a memcmp 51; CHECK-NEXT: Natural Loop Information 52; CHECK-NEXT: Lazy Branch Probability Analysis 53; CHECK-NEXT: Lazy Block Frequency Analysis 54; CHECK-NEXT: Expand memcmp() to load/stores 55; CHECK-NEXT: Lower Garbage Collection Instructions 56; CHECK-NEXT: Shadow Stack GC Lowering 57; CHECK-NEXT: Remove unreachable blocks from the CFG 58; CHECK-NEXT: Natural Loop Information 59; CHECK-NEXT: Post-Dominator Tree Construction 60; CHECK-NEXT: Branch Probability Analysis 61; CHECK-NEXT: Block Frequency Analysis 62; CHECK-NEXT: Constant Hoisting 63; CHECK-NEXT: Replace intrinsics with calls to vector library 64; CHECK-NEXT: Lazy Branch Probability Analysis 65; CHECK-NEXT: Lazy Block Frequency Analysis 66; CHECK-NEXT: Optimization Remark Emitter 67; CHECK-NEXT: Partially inline calls to library functions 68; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining) 69; CHECK-NEXT: Scalarize Masked Memory Intrinsics 70; CHECK-NEXT: Expand reduction intrinsics 71; CHECK-NEXT: Natural Loop Information 72; CHECK-NEXT: CodeGen Prepare 73; CHECK-NEXT: Dominator Tree Construction 74; CHECK-NEXT: Exception handling preparation 75; CHECK-NEXT: Merge internal globals 76; CHECK-NEXT: Natural Loop Information 77; CHECK-NEXT: Scalar Evolution Analysis 78; CHECK-NEXT: Prepare loop for ppc preferred instruction forms 79; CHECK-NEXT: Scalar Evolution Analysis 80; CHECK-NEXT: Lazy Branch Probability Analysis 81; CHECK-NEXT: Lazy Block Frequency Analysis 82; CHECK-NEXT: Optimization Remark Emitter 83; CHECK-NEXT: Hardware Loop Insertion 84; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 85; CHECK-NEXT: Function Alias Analysis Results 86; CHECK-NEXT: ObjC ARC contraction 87; CHECK-NEXT: Prepare callbr 88; CHECK-NEXT: Safe Stack instrumentation pass 89; CHECK-NEXT: Insert stack protectors 90; CHECK-NEXT: Module Verifier 91; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 92; CHECK-NEXT: Function Alias Analysis Results 93; CHECK-NEXT: Natural Loop Information 94; CHECK-NEXT: Post-Dominator Tree Construction 95; CHECK-NEXT: Branch Probability Analysis 96; CHECK-NEXT: Assignment Tracking Analysis 97; CHECK-NEXT: Lazy Branch Probability Analysis 98; CHECK-NEXT: Lazy Block Frequency Analysis 99; CHECK-NEXT: PowerPC DAG->DAG Pattern Instruction Selection 100; CHECK-NEXT: MachineDominator Tree Construction 101; CHECK-NEXT: PowerPC CTR Loops Verify 102; CHECK-NEXT: PowerPC VSX Copy Legalization 103; CHECK-NEXT: Finalize ISel and expand pseudo-instructions 104; CHECK-NEXT: MachineDominator Tree Construction 105; CHECK-NEXT: Machine Natural Loop Construction 106; CHECK-NEXT: PowerPC CTR loops generation 107; CHECK-NEXT: Lazy Machine Block Frequency Analysis 108; CHECK-NEXT: Early Tail Duplication 109; CHECK-NEXT: Optimize machine instruction PHIs 110; CHECK-NEXT: Slot index numbering 111; CHECK-NEXT: Merge disjoint stack slots 112; CHECK-NEXT: Local Stack Slot Allocation 113; CHECK-NEXT: Remove dead machine instructions 114; CHECK-NEXT: MachineDominator Tree Construction 115; CHECK-NEXT: Machine Natural Loop Construction 116; CHECK-NEXT: Machine Trace Metrics 117; CHECK-NEXT: Early If-Conversion 118; CHECK-NEXT: Lazy Machine Block Frequency Analysis 119; CHECK-NEXT: Machine InstCombiner 120; CHECK-NEXT: Machine Block Frequency Analysis 121; CHECK-NEXT: Early Machine Loop Invariant Code Motion 122; CHECK-NEXT: MachineDominator Tree Construction 123; CHECK-NEXT: Machine Block Frequency Analysis 124; CHECK-NEXT: Machine Common Subexpression Elimination 125; CHECK-NEXT: MachinePostDominator Tree Construction 126; CHECK-NEXT: Machine Cycle Info Analysis 127; CHECK-NEXT: Machine code sinking 128; CHECK-NEXT: Peephole Optimizations 129; CHECK-NEXT: Remove dead machine instructions 130; CHECK-NEXT: MachineDominator Tree Construction 131; CHECK-NEXT: PowerPC Reduce CR logical Operation 132; CHECK-NEXT: Remove unreachable machine basic blocks 133; CHECK-NEXT: Live Variable Analysis 134; CHECK-NEXT: MachineDominator Tree Construction 135; CHECK-NEXT: MachinePostDominator Tree Construction 136; CHECK-NEXT: Machine Natural Loop Construction 137; CHECK-NEXT: Machine Block Frequency Analysis 138; CHECK-NEXT: PowerPC MI Peephole Optimization 139; CHECK-NEXT: Remove dead machine instructions 140; CHECK-NEXT: Remove unreachable machine basic blocks 141; CHECK-NEXT: Live Variable Analysis 142; CHECK-NEXT: Slot index numbering 143; CHECK-NEXT: Live Interval Analysis 144; CHECK-NEXT: PowerPC TLS Dynamic Call Fixup 145; CHECK-NEXT: PowerPC TOC Register Dependencies 146; CHECK-NEXT: MachineDominator Tree Construction 147; CHECK-NEXT: Machine Natural Loop Construction 148; CHECK-NEXT: Slot index numbering 149; CHECK-NEXT: Live Interval Analysis 150; CHECK-NEXT: Lazy Machine Block Frequency Analysis 151; CHECK-NEXT: Machine Optimization Remark Emitter 152; CHECK-NEXT: Modulo Software Pipelining 153; CHECK-NEXT: Detect Dead Lanes 154; CHECK-NEXT: Init Undef Pass 155; CHECK-NEXT: Process Implicit Definitions 156; CHECK-NEXT: Remove unreachable machine basic blocks 157; CHECK-NEXT: Live Variable Analysis 158; CHECK-NEXT: MachineDominator Tree Construction 159; CHECK-NEXT: Machine Natural Loop Construction 160; CHECK-NEXT: Eliminate PHI nodes for register allocation 161; CHECK-NEXT: Two-Address instruction pass 162; CHECK-NEXT: Slot index numbering 163; CHECK-NEXT: Live Interval Analysis 164; CHECK-NEXT: Register Coalescer 165; CHECK-NEXT: Rename Disconnected Subregister Components 166; CHECK-NEXT: Machine Instruction Scheduler 167; CHECK-NEXT: PowerPC VSX FMA Mutation 168; CHECK-NEXT: Machine Natural Loop Construction 169; CHECK-NEXT: Machine Block Frequency Analysis 170; CHECK-NEXT: Debug Variable Analysis 171; CHECK-NEXT: Live Stack Slot Analysis 172; CHECK-NEXT: Virtual Register Map 173; CHECK-NEXT: Live Register Matrix 174; CHECK-NEXT: Bundle Machine CFG Edges 175; CHECK-NEXT: Spill Code Placement Analysis 176; CHECK-NEXT: Lazy Machine Block Frequency Analysis 177; CHECK-NEXT: Machine Optimization Remark Emitter 178; CHECK-NEXT: Greedy Register Allocator 179; CHECK-NEXT: Virtual Register Rewriter 180; CHECK-NEXT: Register Allocation Pass Scoring 181; CHECK-NEXT: Stack Slot Coloring 182; CHECK-NEXT: Machine Copy Propagation Pass 183; CHECK-NEXT: Machine Loop Invariant Code Motion 184; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis 185; CHECK-NEXT: Fixup Statepoint Caller Saved 186; CHECK-NEXT: PostRA Machine Sink 187; CHECK-NEXT: Machine Block Frequency Analysis 188; CHECK-NEXT: MachineDominator Tree Construction 189; CHECK-NEXT: MachinePostDominator Tree Construction 190; CHECK-NEXT: Lazy Machine Block Frequency Analysis 191; CHECK-NEXT: Machine Optimization Remark Emitter 192; CHECK-NEXT: Shrink Wrapping analysis 193; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization 194; CHECK-NEXT: Machine Late Instructions Cleanup Pass 195; CHECK-NEXT: Control Flow Optimizer 196; CHECK-NEXT: Lazy Machine Block Frequency Analysis 197; CHECK-NEXT: Tail Duplication 198; CHECK-NEXT: Machine Copy Propagation Pass 199; CHECK-NEXT: Post-RA pseudo instruction expansion pass 200; CHECK-NEXT: MachineDominator Tree Construction 201; CHECK-NEXT: Machine Natural Loop Construction 202; CHECK-NEXT: Machine Block Frequency Analysis 203; CHECK-NEXT: If Converter 204; CHECK-NEXT: MachineDominator Tree Construction 205; CHECK-NEXT: Machine Natural Loop Construction 206; CHECK-NEXT: PostRA Machine Instruction Scheduler 207; CHECK-NEXT: Analyze Machine Code For Garbage Collection 208; CHECK-NEXT: Machine Block Frequency Analysis 209; CHECK-NEXT: MachinePostDominator Tree Construction 210; CHECK-NEXT: Branch Probability Basic Block Placement 211; CHECK-NEXT: Insert fentry calls 212; CHECK-NEXT: Insert XRay ops 213; CHECK-NEXT: Implement the 'patchable-function' attribute 214; CHECK-NEXT: PowerPC Pre-Emit Peephole 215; CHECK-NEXT: PowerPC Early-Return Creation 216; CHECK-NEXT: Contiguously Lay Out Funclets 217; CHECK-NEXT: Remove Loads Into Fake Uses 218; CHECK-NEXT: StackMap Liveness Analysis 219; CHECK-NEXT: Live DEBUG_VALUE analysis 220; CHECK-NEXT: Machine Sanitizer Binary Metadata 221; CHECK-NEXT: Lazy Machine Block Frequency Analysis 222; CHECK-NEXT: Machine Optimization Remark Emitter 223; CHECK-NEXT: Stack Frame Layout Analysis 224; CHECK-NEXT: PowerPC Expand Atomic 225; CHECK-NEXT: PowerPC Branch Selector 226; CHECK-NEXT: Lazy Machine Block Frequency Analysis 227; CHECK-NEXT: Machine Optimization Remark Emitter 228; CHECK-NEXT: Linux PPC Assembly Printer 229; CHECK-NEXT: Free MachineFunction 230 231define void @f() { 232 ret void 233} 234