xref: /llvm-project/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical.ll (revision be4a1dfbf93dcb837e06bb619b934ed8cf9fd224)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple ppc64le-linux -ppc-asm-full-reg-names -global-isel -o - < %s \
3; RUN:     | FileCheck %s
4
5define i64 @test_andi64(i64 %a, i64 %b) {
6; CHECK-LABEL: test_andi64:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    and r3, r3, r4
9; CHECK-NEXT:    blr
10  %res = and i64 %a, %b
11  ret i64 %res
12}
13
14define i64 @test_nandi64(i64 %a, i64 %b) {
15; CHECK-LABEL: test_nandi64:
16; CHECK:       # %bb.0:
17; CHECK-NEXT:    nand r3, r3, r4
18; CHECK-NEXT:    blr
19  %and = and i64 %a, %b
20  %neg = xor i64 %and, -1
21  ret i64 %neg
22}
23
24define i64 @test_andci64(i64 %a, i64 %b) {
25; CHECK-LABEL: test_andci64:
26; CHECK:       # %bb.0:
27; CHECK-NEXT:    andc r3, r3, r4
28; CHECK-NEXT:    blr
29  %neg = xor i64 %b, -1
30  %and = and i64 %a, %neg
31  ret i64 %and
32}
33
34define i64 @test_ori64(i64 %a, i64 %b) {
35; CHECK-LABEL: test_ori64:
36; CHECK:       # %bb.0:
37; CHECK-NEXT:    or r3, r3, r4
38; CHECK-NEXT:    blr
39  %res = or i64 %a, %b
40  ret i64 %res
41}
42
43define i64 @test_orci64(i64 %a, i64 %b) {
44; CHECK-LABEL: test_orci64:
45; CHECK:       # %bb.0:
46; CHECK-NEXT:    orc r3, r3, r4
47; CHECK-NEXT:    blr
48  %neg = xor i64 %b, -1
49  %or = or i64 %a, %neg
50  ret i64 %or
51}
52
53define i64 @test_nori64(i64 %a, i64 %b) {
54; CHECK-LABEL: test_nori64:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    nor r3, r3, r4
57; CHECK-NEXT:    blr
58  %or = or i64 %a, %b
59  %neg = xor i64 %or, -1
60  ret i64 %neg
61}
62
63define i64 @test_xori64(i64 %a, i64 %b) {
64; CHECK-LABEL: test_xori64:
65; CHECK:       # %bb.0:
66; CHECK-NEXT:    xor r3, r3, r4
67; CHECK-NEXT:    blr
68  %res = xor i64 %a, %b
69  ret i64 %res
70}
71